1library IEEE;
2use IEEE.STD_LOGIC_1164.ALL;
3
4entity Multi8 is
5
6
7    port ( X  : in Std_Logic_Vector(7 downto 0) ;
8           Y  : in Std_Logic_Vector(7 downto 0) ;
9           R  : out Std_Logic_Vector(15 downto 0) );
10
11end Multi8;
12
13----------------------------------------------------------------------
14
15architecture beh OF Multi8 is
16
17  signal PP1 : Std_Logic_Vector(8 downto 0);
18  signal PP2 : Std_Logic_Vector(8 downto 0);
19  signal PP3 : Std_Logic_Vector(8 downto 0);
20  signal PP4 : Std_Logic_Vector(8 downto 0);
21  signal PP5 : Std_Logic_Vector(8 downto 0);
22  signal PP6 : Std_Logic_Vector(8 downto 0);
23  signal PP7 : Std_Logic_Vector(8 downto 0);
24  signal PP8 : Std_Logic_Vector(8 downto 0);
25
26  signal PP12 : Std_Logic_Vector(9 downto 0);
27  signal PP34 : Std_Logic_Vector(9 downto 0);
28  signal PP56 : Std_Logic_Vector(9 downto 0);
29  signal PP78 : Std_Logic_Vector(9 downto 0);
30
31  signal R1, R2   : Std_Logic_Vector(11 downto 0);
32
33begin
34
35   PP1(0) <= Y(0) and X(0);
36   PP1(1) <= Y(0) and X(1);
37   PP1(2) <= Y(0) and X(2);
38   PP1(3) <= Y(0) and X(3);
39   PP1(4) <= Y(0) and X(4);
40   PP1(5) <= Y(0) and X(5);
41   PP1(6) <= Y(0) and X(6);
42   PP1(7) <= Y(0) and X(7);
43   PP1(8) <= '0';
44
45   PP2(0) <= '0';
46   PP2(1) <= Y(1) and X(0);
47   PP2(2) <= Y(1) and X(1);
48   PP2(3) <= Y(1) and X(2);
49   PP2(4) <= Y(1) and X(3);
50   PP2(5) <= Y(1) and X(4);
51   PP2(6) <= Y(1) and X(5);
52   PP2(7) <= Y(1) and X(6);
53   PP2(8) <= Y(1) and X(7);
54
55   PP3(0) <= Y(2) and X(0);
56   PP3(1) <= Y(2) and X(1);
57   PP3(2) <= Y(2) and X(2);
58   PP3(3) <= Y(2) and X(3);
59   PP3(4) <= Y(2) and X(4);
60   PP3(5) <= Y(2) and X(5);
61   PP3(6) <= Y(2) and X(6);
62   PP3(7) <= Y(2) and X(7);
63   PP3(8) <= '0';
64
65   PP4(0) <= '0';
66   PP4(1) <= Y(3) and X(0);
67   PP4(2) <= Y(3) and X(1);
68   PP4(3) <= Y(3) and X(2);
69   PP4(4) <= Y(3) and X(3);
70   PP4(5) <= Y(3) and X(4);
71   PP4(6) <= Y(3) and X(5);
72   PP4(7) <= Y(3) and X(6);
73   PP4(8) <= Y(3) and X(7);
74
75   PP5(0) <= Y(4) and X(0);
76   PP5(1) <= Y(4) and X(1);
77   PP5(2) <= Y(4) and X(2);
78   PP5(3) <= Y(4) and X(3);
79   PP5(4) <= Y(4) and X(4);
80   PP5(5) <= Y(4) and X(5);
81   PP5(6) <= Y(4) and X(6);
82   PP5(7) <= Y(4) and X(7);
83   PP5(8) <= '0';
84
85   PP6(0) <= '0';
86   PP6(1) <= Y(5) and X(0);
87   PP6(2) <= Y(5) and X(1);
88   PP6(3) <= Y(5) and X(2);
89   PP6(4) <= Y(5) and X(3);
90   PP6(5) <= Y(5) and X(4);
91   PP6(6) <= Y(5) and X(5);
92   PP6(7) <= Y(5) and X(6);
93   PP6(8) <= Y(5) and X(7);
94
95   PP7(0) <= Y(6) and X(0);
96   PP7(1) <= Y(6) and X(1);
97   PP7(2) <= Y(6) and X(2);
98   PP7(3) <= Y(6) and X(3);
99   PP7(4) <= Y(6) and X(4);
100   PP7(5) <= Y(6) and X(5);
101   PP7(6) <= Y(6) and X(6);
102   PP7(7) <= Y(6) and X(7);
103   PP7(8) <= '0';
104
105   PP8(0) <= '0';
106   PP8(1) <= Y(7) and X(0);
107   PP8(2) <= Y(7) and X(1);
108   PP8(3) <= Y(7) and X(2);
109   PP8(4) <= Y(7) and X(3);
110   PP8(5) <= Y(7) and X(4);
111   PP8(6) <= Y(7) and X(5);
112   PP8(7) <= Y(7) and X(6);
113   PP8(8) <= Y(7) and X(7);
114
115   PP12 <= PP1 + PP2;
116   PP34 <= PP3 + PP4;
117   PP56 <= PP5 + PP6;
118   PP78 <= PP7 + PP8;
119
120   R1 <= ("00" & PP12) + (PP34 & "00");
121   R2 <= ("00" & PP56) + (PP78 & "00");
122   R <= ("0000" & R1)   + (R2 & "0000");
123
124end beh;
125