1 #include <genlib.h>
2
3 #define POWER "vdd", "vss", 0
4 #define getbit(val,bit) ( ((val) >> (bit))%2 )
5
6 /* + */
fastname(char * deb,char indice,char * reste)7 char *fastname(char *deb,char indice,char *reste)
8 {
9 static char name[100];
10 sprintf(name,"%s%c%s",deb,indice,reste);
11 return name;
12 }
fastname1(char * deb,char indice,char * reste)13 char *fastname1(char *deb,char indice,char *reste)
14 {
15 static char name[100];
16 sprintf(name,"%s%c%s",deb,indice,reste);
17 return name;
18 }
19
20
21 /*******************************************************************/
22
main()23 main()
24 {
25 long i;
26
27
28 GENLIB_DEF_LOFIG("amd2901_ctl");
29
30
31 /* ***************** Terminal Declarations ****************** */
32
33
34 /* Input/Output from and to the data-path. */
35
36 /* Command for selecting operands R and S. */
37
38 GENLIB_LOCON("ops_mx[2:0]", OUT, "ops_mx[2:0]");
39 GENLIB_LOCON("opr_mx[1:0]", OUT, "opr_mx[1:0]");
40
41
42 /* ALU commands and auxiliary terminals. */
43
44 GENLIB_LOCON("alu_k[4:0]", OUT, "alu_k[4:0]");
45 GENLIB_LOCON("alu_cout" , IN , "alu_cout" );
46 GENLIB_LOCON("alu_over" , IN , "alu_over" );
47
48
49 /* RAM, ACCU shifter commands and auxiliary terminals.
50 * ("acc_sh" is same as "ram_sh")
51 */
52
53 GENLIB_LOCON("ram_sh[1:0]", OUT, "ram_sh[1:0]");
54
55 /* Output multiplexer commnand (for X bus). */
56
57 GENLIB_LOCON("out_mx", OUT, "out_mx");
58
59
60 /* ACCU controls terminals.
61 * ("acc_ck", "acc_test" and "acc_scin" directly comes from the plots)
62 */
63
64 GENLIB_LOCON("acc_wen" , OUT, "acc_wen" );
65
66
67 /* Data bus terminals. */
68
69 GENLIB_LOCON( "alu_f[3:0]", IN, "alu_f[3:0]");
70 GENLIB_LOCON("alu_np[3:0]", IN, "alu_np[3:0]");
71 GENLIB_LOCON("alu_ng[3:0]", IN, "alu_ng[3:0]");
72
73
74 /* Input/Output from and to the plots. */
75
76 /* Test terminals from/to plots. */
77
78 GENLIB_LOCON("core_test", IN , "core_test");
79 GENLIB_LOCON("core_fonc", IN , "core_fonc");
80
81
82 /* ALU terminals from/to plots. */
83
84 /* GENLIB_LOCON("core_cout", OUT, "core_cout"); */
85 GENLIB_LOCON("core_np" , OUT, "core_np" );
86 GENLIB_LOCON("core_ng" , OUT, "core_ng" );
87 GENLIB_LOCON("core_over", OUT, "core_over");
88 GENLIB_LOCON("core_zero", OUT, "core_zero");
89
90
91 /* RAM, ACCU shifter terminals from/to plots.
92 * RAM and ACCU I/O plots controls.
93 */
94
95 GENLIB_LOCON("core_sh_right" , OUT, "core_sh_right" );
96 GENLIB_LOCON("core_sh_left" , OUT, "core_sh_left" );
97
98
99 /* Data bus terminals from/to the plots. */
100
101 GENLIB_LOCON("i[8:0]", IN , "i[8:0]");
102
103 GENLIB_LOCON("noe", IN , "noe");
104 GENLIB_LOCON("oe", OUT , "oe");
105
106 /* + */
107
108 GENLIB_LOCON("a[3:0]", IN, "a[3:0]");
109 GENLIB_LOCON("b[3:0]", IN, "b[3:0]");
110 // GENLIB_LOCON("wb[3:0]", OUT, "wb[3:0]");
111
112 GENLIB_LOCON("deca[15:0]", OUT, "deca[15:0]");
113 GENLIB_LOCON("decb[15:0]", OUT, "decb[15:0]");
114 GENLIB_LOCON("decwb[15:0]", OUT, "decwb[15:0]");
115
116 /* - */
117
118 // GENLIB_LOCON("ram_wri", OUT, "ram_wri");
119
120
121 /* Power supply connectors. */
122
123 GENLIB_LOCON("vdd", IN , "vdd");
124 GENLIB_LOCON("vss", IN , "vss");
125
126
127 /* + */
128
129 /* decoders for RAM RA and RB addresses. */
130 GENLIB_LOINS ("inv_x4", "inv_a0", "a[0]", "na[0]", "vdd", "vss", NULL);
131 GENLIB_LOINS ("inv_x4", "inv_a1", "a[1]", "na[1]", "vdd", "vss", NULL);
132 GENLIB_LOINS ("inv_x4", "inv_a2", "a[2]", "na[2]", "vdd", "vss", NULL);
133 GENLIB_LOINS ("inv_x4", "inv_a3", "a[3]", "na[3]", "vdd", "vss", NULL);
134
135 GENLIB_LOINS ("inv_x4", "inv_b0", "b[0]", "nb[0]", "vdd", "vss", NULL);
136 GENLIB_LOINS ("inv_x4", "inv_b1", "b[1]", "nb[1]", "vdd", "vss", NULL);
137 GENLIB_LOINS ("inv_x4", "inv_b2", "b[2]", "nb[2]", "vdd", "vss", NULL);
138 GENLIB_LOINS ("inv_x4", "inv_b3", "b[3]", "nb[3]", "vdd", "vss", NULL);
139
140 GENLIB_LOINS ("inv_x4", "inv_wen", "ram_wri", "ram_nwen", "vdd", "vss", NULL);
141 for (i = 0; i < 16; i++)
142 {
143 GENLIB_LOINS ("na4_x1", GENLIB_NAME ("na4_ram_adrb_%d_0", i),
144 GENLIB_NAME ("%s[3]", (getbit (i, 3) ? "b" : "nb")),
145 GENLIB_NAME ("%s[2]", (getbit (i, 2) ? "b" : "nb")),
146 GENLIB_NAME ("%s[1]", (getbit (i, 1) ? "b" : "nb")),
147 GENLIB_NAME ("%s[0]", (getbit (i, 0) ? "b" : "nb")),
148 GENLIB_NAME ("ram_adrb_%d",i),
149 "vdd", "vss", NULL);
150
151 GENLIB_LOINS ("inv_x2", GENLIB_NAME ("n1_ram_adrb_%d_1",i),
152 GENLIB_NAME ("ram_adrb_%d", i),
153 GENLIB_ELM ("decb", i),
154 "vdd", "vss", NULL);
155
156 GENLIB_LOINS ("no2_x1", GENLIB_NAME ("no2_ram_adri_%d_0",i),
157 GENLIB_NAME ("ram_adrb_%d", i),
158 "ram_nwen",
159 GENLIB_ELM ("decwb", i),
160 "vdd", "vss", NULL);
161
162 GENLIB_LOINS ("a4_x2", GENLIB_NAME ("a4_ram_adra_%d_0",i),
163 GENLIB_NAME("%s[3]", (getbit (i, 3) ? "a" : "na")),
164 GENLIB_NAME("%s[2]", (getbit (i, 2) ? "a" : "na")),
165 GENLIB_NAME("%s[1]", (getbit (i, 1) ? "a" : "na")),
166 GENLIB_NAME("%s[0]", (getbit (i, 0) ? "a" : "na")),
167 GENLIB_ELM("deca", i),
168 "vdd", "vss", NULL);
169 }
170
171 /* - */
172
173 /* ***************** S multiplexer control ****************** */
174
175
176 GENLIB_LOINS("inv_x1", "n1_i2", "i[2]", "ni[2]", POWER);
177 GENLIB_LOINS("inv_x1", "n1_i1", "i[1]", "ni[1]", POWER);
178 GENLIB_LOINS("inv_x1", "n1_i0", "i[0]", "ni[0]", POWER);
179
180 GENLIB_LOINS("no2_x1", "no2_ops_mx0", "i[2]", "ni[0]", "ops_mx[0]", POWER);
181 GENLIB_LOINS("no2_x1", "no2_ops_mx1", "ni[2]", "i[1]", "ops_mx[1]", POWER);
182 GENLIB_LOINS( "a3_x2", "a3_ops_mx2", "i[2]", "i[1]", "i[0]", "ops_mx[2]", POWER);
183
184
185 /* ***************** R multiplexer control ****************** */
186
187
188 GENLIB_LOINS( "o2_x2", "o2_opr_mx0" , "i[2]", "i[1]", "opr_mx[0]", POWER);
189 GENLIB_LOINS("na2_x1", "na2_opr_mx1_0", "ni[2]", "i[1]", "opr_mx1_0", POWER);
190 GENLIB_LOINS("na3_x1", "na3_opr_mx1_1", "i[2]", "ni[1]", "ni[0]","opr_mx1_1", POWER);
191 GENLIB_LOINS("na2_x1", "na2_opr_mx1_2", "opr_mx1_0","opr_mx1_1","opr_mx[1]", POWER);
192
193
194 /* ***************** X multiplexer control ****************** */
195
196 GENLIB_LOINS("inv_x1", "n1_i3", "i[7]", "ni[3]", POWER);
197 GENLIB_LOINS("no3_x1", "no3_out_mx0", "i[8]", "ni[3]", "i[6]", "out_mx", POWER);
198
199
200 /* ********************** ALU control *********************** */
201
202
203 /* ALU commands. */
204 GENLIB_LOINS("xr2_x1", "xr2_alu_k0", "i[5]", "i[3]", "alu_k[0]", POWER);
205 GENLIB_LOINS("xr2_x1", "xr2_alu_k1", "i[5]", "i[4]", "alu_k[1]", POWER);
206 GENLIB_LOINS( "inv_x1", "n1_i4", "i[4]", "ni[4]", POWER);
207 GENLIB_LOINS( "a2_x2", "a2_alu_k2", "i[5]", "ni[4]", "alu_k[2]", POWER);
208 GENLIB_LOINS( "inv_x1", "n1_i5", "i[5]", "ni[5]", POWER);
209 GENLIB_LOINS( "a3_x2", "a3_alu_k3", "ni[5]","i[4]","i[3]","alu_k[3]", POWER);
210 GENLIB_LOINS( "a2_x2", "a2_alu_k4", "i[4]", "i[3]", "alu_k4_0", POWER);
211 GENLIB_LOINS( "o2_x2", "o2_alu_k4", "alu_k4_0", "i[5]", "alu_k[4]", POWER);
212
213 /* Compute of ALU flags.
214 * Propagate.
215 */
216
217 GENLIB_LOINS("no2_x1", "no2_alu_p_0", "alu_np[0]", "alu_np[1]", "alu_p_0", POWER);
218 GENLIB_LOINS("no2_x1", "no2_alu_p_1", "alu_np[2]", "alu_np[3]", "alu_p_1", POWER);
219 GENLIB_LOINS("na2_x1", "na2_alu_p", "alu_p_0", "alu_p_1", "core_np", POWER);
220
221 /* Generate. */
222 GENLIB_LOINS("no2_x1", "no2_alu_g_0", "alu_np[1]", "alu_ng[0]", "alu_g_0", POWER);
223 GENLIB_LOINS("no2_x1", "no2_alu_g_1", "alu_np[3]", "alu_np[2]", "alu_g_1", POWER);
224 GENLIB_LOINS( "inv_x1", "n1_alu_g_2", "alu_ng[1]", "alu_g_2", POWER);
225
226 GENLIB_LOINS("noa22_x1", "noa3_alu_g_3", "alu_np[3]","alu_ng[2]","alu_ng[3]","alu_g_3" , POWER);
227 GENLIB_LOINS( "inv_x1", "n1_alu_g_4", "alu_g_3" , "alu_g_4", POWER);
228
229 GENLIB_LOINS("na2_x1", "na2_alu_g_5", "alu_g_0", "alu_g_1", "alu_g_5", POWER);
230 GENLIB_LOINS("na2_x1", "na2_alu_g_6", "alu_g_1", "alu_g_2", "alu_g_6", POWER);
231
232 GENLIB_LOINS("a3_x2", "na3_alu_g_7", "alu_g_4",
233 "alu_g_5",
234 "alu_g_6",
235 "core_ng" , POWER);
236
237 /* Zero and overflow */
238
239 GENLIB_LOINS("no2_x1", "no2_alu_zero_0", "alu_f[0]", "alu_f[1]", "alu_zero_0", POWER);
240 GENLIB_LOINS("no2_x1", "no2_alu_zero_1", "alu_f[2]", "alu_f[3]", "alu_zero_1", POWER);
241 GENLIB_LOINS("a2_x2", "a2_alu_zero", "alu_zero_0", "alu_zero_1", "core_zero", POWER);
242
243 GENLIB_LOINS("xr2_x1", "nxr2_alu_nover", "alu_over",
244 "alu_cout", "core_over", POWER);
245
246
247 /* ********************* ACCU control *********************** */
248
249
250 GENLIB_LOINS("inv_x1", "n1_i6", "i[8]", "ni[6]", POWER);
251
252 /* Compute of ACCU write enable. */
253 GENLIB_LOINS("noa22_x1", "nao3_acc_wen", "ni[6]",
254 "i[7]",
255 "i[6]",
256 "acc_wen" , POWER);
257
258
259 /* ********************** RAM control *********************** */
260
261
262 /* ACCU and RAM shift multiplexer control. */
263 GENLIB_LOINS("na2_x1", "na2_ram_sh0", "i[8]", "i[7]", "ram_sh[0]", POWER);
264 GENLIB_LOINS( "inv_x1", "n1_ram_sh1", "i[8]", "ram_sh[1]", POWER);
265
266 /* RAM and ACCU I/O plots controls. */
267 GENLIB_LOINS("a2_x2","a2_core_sh_left" ,"i[8]", "i[7]","core_sh_left" ,POWER);
268 GENLIB_LOINS("a2_x2","a2_core_sh_right","i[8]","ni[3]","core_sh_right",POWER);
269
270 /* Compute of RAM write enable. */
271 GENLIB_LOINS( "inv_x1", "n1_ram_nwri_0", "core_fonc", "core_nfonc", POWER);
272 GENLIB_LOINS( "no2_x1", "no2_ram_nwri_1", "core_test", "core_nfonc",
273 "fonc_mode" , POWER);
274 GENLIB_LOINS("noa22_x1", "noa3_ram_nwri_2", "i[8]",
275 "i[7]",
276 "fonc_mode" ,
277 "ram_nwri" , POWER);
278 GENLIB_LOINS("inv_x1","inv_ram_wri","ram_nwri","ram_wri", POWER );
279
280 GENLIB_LOINS( "inv_x1","inv_noe","noe","oe", POWER);
281
282 GENLIB_SAVE_LOFIG();
283
284 exit(0);
285 }
286
287
288