1`ifndef __SHARE_CASCADE_STDLIB_STDLIB_V 2`define __SHARE_CASCADE_STDLIB_STDLIB_V 3 4/////////////////////////////////////////////////////////////////////////////// 5// 6// This file contains declarations for the cascade standard library. The names 7// of these modules are reserved by cascade and cannot be overriden by user 8// programs. Target-specific backend implementations are expected to provide a 9// march file which instantiates whichever of these modules that backend 10// supports and to provide appropriate annotations for those instantiations. 11// At a minimum, a target-specific implementation must instantiate both the 12// Root and the global clock. 13// 14// All of the modules in the standard library support the following 15// annotations. Additional module-specific annotations are discussed below. 16// 17// __target = "..." 18// Required. Tells the compiler class which core compiler to use. Providing a 19// second target, separated by a semi-colon, tells the compiler class which 20// core compiler to use during second pass compilation. 21// __loc = "..." 22// Optional. Tells the compiler class which interface compiler to use. If 23// not provided, defaults to "local", ie in the same process space as the 24// runtime. Providing a second location, separated by a semi-colon, tells the 25// compiler class which core compiler to use during second pass compilation. 26// 27/////////////////////////////////////////////////////////////////////////////// 28 29/////////////////////////////////////////////////////////////////////////////// 30// Minimal Implementation: 31/////////////////////////////////////////////////////////////////////////////// 32 33// The top-level module. Evaluated module items are inserted here. 34(*__std="logic", __loc="local", __target="sw"*) 35module Root(); 36 localparam STDIN = 32'h8000_0000; 37 localparam STDOUT = 32'h8000_0001; 38 localparam STDERR = 32'h8000_0002; 39 localparam STDWARN = 32'h8000_0003; 40 localparam STDINFO = 32'h8000_0004; 41 localparam STDLOG = 32'h8000_0005; 42endmodule 43 44// The top-level virtual clock. 45(*__std="clock", __loc="local", __target="sw"*) 46module Clock( 47 output wire val 48); 49 50 // Possible Implementation: 51 // 52 // output reg val = 0; 53 // always @(val) begin 54 // #1; val <= ~val; 55 // end 56 57endmodule 58 59/////////////////////////////////////////////////////////////////////////////// 60// Target-Specific Components: 61/////////////////////////////////////////////////////////////////////////////// 62 63// The top-level reset signal 64(*__std="reset"*) 65module Reset( 66 output wire val 67); 68 69 // Possible Implementation: 70 // 71 // output wire val = <reset pin>; 72 73endmodule 74 75// An arbitrary width source of binary inputs 76(*__std="pad"*) 77module Pad#( 78 parameter WIDTH = 4 79)( 80 output wire[WIDTH-1:0] val 81); 82 83 // Possible Implementation: 84 // 85 // output wire[WIDTH-1:0] val = <pad pins>; 86 87endmodule 88 89// An arbitrary width source of binary outputs 90(*__std="led"*) 91module Led#( 92 parameter WIDTH = 8 93)( 94 input wire[WIDTH-1:0] val 95); 96 97 // Possible Implementation: 98 // 99 // input wire[WIDTH-1:0] val; 100 // assign <led pins> = val; 101 102endmodule 103 104// An arbitrary width source of binary outputs 105(*__std="gpio"*) 106module Gpio#( 107 parameter WIDTH = 8 108)( 109 input wire[WIDTH-1:0] val 110); 111 112 // Possible Implementation: 113 // 114 // input wire[WIDTH-1:0] val; 115 // assign <gpio pins> = val; 116 117endmodule 118 119/////////////////////////////////////////////////////////////////////////////// 120 121`endif 122