1160614_1505 Add box handling 2 Add parasitic diodes (just the setting) 3160721_1627 When reporting shorts to limited voltages, include the reason 4 Include calculated bit flags when reporting calculated biases 5 Added path contains check 6 Fixed bulk check to ignore errors to same levels that are actually open 7 Changed lock file removal 8 Ignore empty instances 9 Changed default for open nets in calculated power (all queues -> only current queue) 10160816_1822 Split model error lines 11 Already set voltage errors between defined power fix. (wasn't printing all errors) 12160819_2315 Added ExceedsLeakLimit macro for leak limit checks. 13 Change current limit granularity uA -> nA. 14 Filter 'mos diode min/max voltage already set' errors by current. 15160820_0954 Print progress when processing switches. 16 Shorted device count bug fix (was counting switches/cell. Now counts switches/instance.) 17160823_1132 New lines when printing shorted switches. 18 Don't adjust mos diode resistance when calculating leak current. 19 Fixed progress count for switch shorts. 20 Make sure power exists before checking for HI-Z. 21 Changed equivalent net processing. 22160823_1344 Improved equivalent net processing. 23160824_1750 Fixed fast equivalent net processing. 24160825_1209 Print estimated current in already set min/max (+bug fix in min) 25160829_1200 Move min/max voltage conflict to error processing. 26160830_0001 Added summary line after resistor propagation. 27160906_1035 Include resistor calculation in initial simulation propagation. 28160909_1219 Print interactive commands to log file. 29 Read commands from batch file (source). 30 Removed shortfile. 31161013_1022 Ignore shorts at vth when gate is not calculated(ie. power. If actual leaks exist, they should be detected elsewhere). 32161021_1301 No voltage calculations for Hi-Z nets in any min/max queues. 33 No leaks between Hi-Z nets. 34161110_1402 When checking power families, check family intersect. 35161116_1112 Leak path between 2 Hi-Z nets should not be automatically ignored (only if related). 36 When coping power, copy powerAliases and relativeSets 37 Don't copy family when using macros (powerAlias should be sufficient) 38 When checking relatives, check powerAliases too 39161116_1254 Don't do mos diode calculations for HI-Z voltages 40161117_1005 Reduce relative check time 41 Standardize empty string checks 42161118_1233 Copy family when using macros. (see 161116_1112) 43 Only print unexpected power for possible problems (lower min voltage, higher max voltage) 44 Display log file name at job end 45 Remove short file message (unused) 46 PrintEnvironment interactive command output to log file. 47 Remove net progress on min/max queues 48 Overwrite progress displays 49 Changed progess print count logic(except event queue) 50 Flush interactive output before new command 51161208_0148 Fixed bug that missed gate errors on tied output. 52161219_2241 Fixed loop with no default voltage for calculated voltages 53 Switched line reset to print after instead of before 54161221_1201 Changed unexpected mos diode errors to debug mode 55 Don't calculate resistance for Hi-Z nets 56 Display mismatched net error in detail 57170216_1137 Changed cvcrc.default -> default.cvcrc 58170327_2128 More info in interactive net displays #45 59 Fixed max voltage bug in expected open error display 60 Added Vth macro for power calculations #2, #34 61 Moved initial model/power file load to before netlist load #2, #34 62 Fixed expected value check to include actual net in addition to alias #56 63 Auto create macros for top level nets that aren't ports 64170405_1431 Added SCRC handling 65 Added traceinverter command to interactive 66 Added findnet command to search for net matches to interactive 67 Initialize instance pointers to NULL (for empty instances) 68 Print connection stats for equivalent nets 69170406_1251 SCRC fixes and power mos settings 70 Cell name filters for models 71170412_0102 Save calculated leak voltage (bug fix) 72 Print leak voltages in interactive 73 Print cell filters even when there are no conditions (bug fix) 74 Remove model lookup based on parameters (not possible with cell name filter) 75 Print overvoltage limit formula and calculation, along with model conditions for overvoltage errors 76 SCRC net calculation for power mos gate (bug fix) 77 Standardized and simplified power calculation printing 78170421_1414 Changed Vth flag in current calculation to reduce false leak errors(cludge) 79 Don't report shorts to open power if permitted relative 80 Changed SCRC processing to work with all logic nets, not just inverters 81 Errors generated when can't set SCRC net 82 SCRC nets should not be flagged as calculated 83170427_1824 Don't show shorts at vth difference with clamped nets 84 Don't adjust open voltages in simulation propagation 85 Count attempts and not actual changes for SCRC nodes 86 Renamed IsSCRCNet -> IsSCRCLogicNet 87 Added function to count active connections 88 Added secondary Hi-Z gate check to detect floating nets due to floating gate input 89 In SCRC mode, set input for all open power mos (not just SCRC power mos) 90 In SCRC mode, if can not set gate net, set the current net 91 When setting power for power mos gates, ignore relatives 92 When checking for SCRC logic, make sure one of the power nets is SCRC 93 When checking for leak paths, ignore paths to calculated voltages caused by the device 94 Corrected spelling CvdDb_p -> CvcDb_p 95 When setting calculated sim voltage, grab alias from min/max default 96170504_1251 Print resistor calculations to log only 97 Equations allow SI notation 98 Fixed calculated bias printing 99170508_1111 Added device count routine 100 Propagate power through power resistors 101 No missing bias errors if min/max defined for sim power 102170510_1640 Detect possible leaks between simulation voltages and open voltages 103 Added interactive debug command for module debugging 104 DeviceCount only counts devices in specified instance 105 Added gate and bulk counts to DeviceCount 106 Added DeviceCount print routine 107 Added subroutines to calculate depth and check inclusion in subcircuit 108 Added "calculation=>" string to resistor definition to differentiate between original definition and calculation 109 In interactive, changing to invalid instance returns an error and doesn't change current instance 110 Debug power files have "NO AUTO MACROS" that don't automatically create macro from power definitions 111 Added UNKNOWN_INSTANCE definition 112170512_1049 Added abitlity to skip error extraction for debugging 113 Changed debug command to use unique mode name 114 Enable interrupt of interactive commands (currently findnet only) 115 Added 3 terminal capacitor cdl output 116 Print leak voltage even if normal voltage is unknown 117170821_0958 Leak voltages override unknown min/max in overvoltage error display 118 Changed FloatingNet routine to not include PossibleHi-Z errors 119 Possible HiZ errors shouldn't cause secondary Hi-Z errors 120 Added message for tri-state input 121 Changed HasLeak routine to ignore partial calculated voltages 122170822_0026 SCRC power to output is error 123 Propagate SCRC power 124 Bug fix for smashed hierarchy devices 125 Include pointer check in IsSCRCPower for simplicity (slower) 126 For SCRC sim power values, use min/max 127 No leak if source/drain has no min/max 1280.9.0 Changed mail address to cvc at shuharisystem dot com 129 Fixed logic comparison bug 1300.9.1 Bug: Logic on min path greater than logic on max path 131 Bug: Calculating expected SCRC voltage ignored user setting 132 Bug: Virtual net count exceeded loop count causing abort. Increased loop count. 133 Added target net display when calculating SCRC nets 1340.10.9 Bug: Add flag to ignore Hi-Z when calculating min/max 135 Bug: Check both MIN/MAX flag logic error 136 Bug: Constant and pointer check fixes 137 Bug: debug power value fix 138 Bug: Fixed connection counts. 139 Bug: Hi-Z voltages should not activate min/max voltages 140 Bug: Ignore sim limits on first sim propagation 141 Bug: Logic problem for non-conducting resistors (ignored power connections) 142 Bug: MIN = MAX fuse errors check nets, not voltages. only print to log file(not display). 143 Bug: Min/max checks also set pull-up/down. 144 Bug: No shorts from Hi-Z to expected power 145 Bug: No voltage change for Hi-Z power in second min/max propagation 146 Bug: non SCRC Hi-Z conflicts should yield error 147 Bug: Only reroute priority devices. Always reroute direct connections. Don't propagate direct connection. 148 Bug: Prevent Vth drops back through mos. 149 Bug: Process fuse last 150 Bug: Recount connection fix 151 Bug: Restrict always on mos to non-ouput or low relative resistance. 152 Bug: Restrict MIN/MAX checks to relevant devices 153 Bug: Save pull-up/down voltages for subsequent min/max checks. 154 Bug: Shorts between calculated expected voltages should be flagged regardless of current 155 Bug: Use default min/max path to avoid false leakpath errors in Hi-Z check 156 Bug: Use first min/max voltages to validate second min/max voltages 157 Bug: Vth voltage drops should not cause leak current. 158 Bug: When calculating min/max in 2nd pass, use leak as well as sim voltage, and set default. 159 Bug: When copying power definitions, include family info 160 Bug: When resetting min/max after sim, don't use sim if min/max would be invalid. 161 Cha: Always save initial voltages 162 Cha: debug log file name 163 Cha: Improved duplicate power definition error display 164 Cha: Improved SCRC power warnings 165 Cha: Leak voltages do not override unknown min/max for overvoltage 166 Cha: No possible leak errors for always off gates 167 Cha: Overvoltage errors for logic levels don't include unknown voltages 168 Cha: Reduce mos bias false errors 169 Cha: Sim shorts print all connections instead of just sim 170 Eff: Added DefaultMin/Max routines 171 Eff: Added routine to check reroute and routine to calculate propagation priority 172 Eff: Centralized flags to check for min/max voltage validity 173 Eff: Skip power nets in trvial min/max calculations 174 Enh: Added parameter flags for leakOvervoltage, logicDiodes, vthGates 175 Enh: Added routine to calculate relative voltage 176 Enh: Added routines to prevent HiZ power propagation 177 Enh: Option to ignore Vth differences on gate-source connections 178 Enh: Option to only use logic values for overvoltage 179 Enh: Option to prefer logic values for diode checks 180 Enh: Print short summary once after all latch processing. 181 Enh: Propagate through latches if both voltages the same 1820.11.3 Enh: Add threshold parameter to filter errors 183 Bug: Set expected min/max for off mos, too 184 Bug: SKIP_QUEUE was being processed 185 Bug: Latch setting bug 186 Enh: Added expandnet to interactive 187 Bug: Display message for unimplemented commands 188 Bug: Looping when setting virtual vector 189 Bug: Unknown min/max abort 190