1library	ieee;
2use		ieee.std_logic_1164.all;
3--use		ieee.std_logic_arith.all;
4
5package definitions is
6
7-- flag bits
8constant	carry_bit:				integer := 0;
9constant	add_sub_bit:			integer := 1;
10constant	parity_overflow_bit:	integer := 2;
11constant	half_carry_bit:	  		integer := 4;
12constant	zero_bit:		  		integer := 6;
13constant	sign_bit:		  		integer := 7;
14
15-- 8 bit register numbers
16constant	B:				  		std_logic_vector(3 downto 0)	:= "0000";
17constant	B3:						std_logic_vector(2 downto 0)	:= "000";	-- keep GHDL happy,
18																				-- won't accept
19																				-- bitslice of
20																				-- constant in case
21																				-- statements
22constant	C:				  		std_logic_vector(3 downto 0)	:= "0001";
23constant	C3:						std_logic_vector(2 downto 0)	:= "001";
24constant	D:				  		std_logic_vector(3 downto 0)	:= "0010";
25constant	D3:						std_logic_vector(2 downto 0)	:= "010";
26constant	E:				  		std_logic_vector(3 downto 0)	:= "0011";
27constant	E3:						std_logic_vector(2 downto 0)	:= "011";
28constant	H:				  		std_logic_vector(3 downto 0)	:= "0100";
29constant	H3:						std_logic_vector(2 downto 0)	:= "100";
30constant	L:				  		std_logic_vector(3 downto 0)	:= "0101";
31constant	L3:						std_logic_vector(2 downto 0)	:= "101";
32constant	memory_register:  		std_logic_vector(3 downto 0)	:= "0110";
33constant	memory_register3:		std_logic_vector(2 downto 0)	:= "110";
34constant	A:			   	  		std_logic_vector(3 downto 0)	:= "0111";
35constant	A3:						std_logic_vector(2 downto 0)	:= "111";
36
37constant	one_register:  	  		std_logic_vector(3 downto 0)	:= "1000";	-- fixed constant of
38																				-- one at register 8
39																				-- in secondary ALU
40																				-- register file
41
42
43constant	zero_register: 	  		std_logic_vector(3 downto 0)	:= "1001";
44constant	indexhigh:	   	  		std_logic_vector(3 downto 0)	:= "1010";
45constant	indexlow:	   	   		std_logic_vector(3 downto 0)	:= "1011";
46constant	bitreg:			   		std_logic_vector(3 downto 0)	:= "1100";
47constant	not_bitreg:		   		std_logic_vector(3 downto 0)	:= "1101";
48constant	SPhigh:		   	   		std_logic_vector(3 downto 0)	:= "1110";
49constant	SPlow:		   	   		std_logic_vector(3 downto 0)	:= "1111";
50
51constant	call_return_interrupt:	std_logic_vector(3 downto 0)	:= "1000";	-- for sending call
52																				-- return address
53																				-- thru ALU, primary
54																				-- register only
55constant	flags_register:	   		std_logic_vector(3 downto 0)	:= "1000";	-- for sending flags
56																				-- thru ALU -
57																				-- multiplexed with
58																				-- call return,
59																				-- primary register
60																				-- only
61constant	interrupt_register:		std_logic_vector(3 downto 0)	:= "1000";	-- for sending
62																				-- interrupt
63																				-- register thru
64																				-- ALU - multiplexed
65																				-- with call return,
66																				-- primary register
67																				-- only
68
69
70
71-- ALU operation codes
72constant	add_operation: 	 		std_logic_vector(4 downto 0)	:= "00000";	-- add without carry
73constant	adc_operation: 	 		std_logic_vector(4 downto 0)	:= "00001";	-- add with carry
74constant	sub_operation: 			std_logic_vector(4 downto 0)	:= "00010";	-- subtract without
75																				-- carry
76constant	sbc_operation: 			std_logic_vector(4 downto 0)	:= "00011";	-- subtract with
77																				-- carry
78constant	and_operation: 			std_logic_vector(4 downto 0)	:= "00100";	-- and
79constant	xor_operation: 			std_logic_vector(4 downto 0)	:= "00101";	-- xor
80constant	or_operation:  			std_logic_vector(4 downto 0)	:= "00110";	-- or
81constant	cmp_operation: 			std_logic_vector(4 downto 0)	:= "00111";	-- compare (subtract
82																				-- and discard
83																				-- results, set
84																				-- flags
85constant	rlc_operation: 			std_logic_vector(4 downto 0)	:= "01000";	-- RLC
86constant	rrc_operation: 			std_logic_vector(4 downto 0)	:= "01001";	-- RRC
87constant	rl_operation: 			std_logic_vector(4 downto 0)	:= "01010";	-- RLA
88constant	rr_operation: 			std_logic_vector(4 downto 0)	:= "01011";	-- RRA
89constant	daa_operation: 			std_logic_vector(4 downto 0)	:= "01100";	-- DAA
90constant	cpl_operation: 			std_logic_vector(4 downto 0)	:= "01101";	-- CPL
91constant	scf_operation: 			std_logic_vector(4 downto 0)	:= "01110";	-- SCF
92constant	ccf_operation: 			std_logic_vector(4 downto 0)	:= "01111";	-- CCF
93constant	sla_operation: 			std_logic_vector(4 downto 0)	:= "10000";	-- SLA
94constant	sra_operation: 			std_logic_vector(4 downto 0)	:= "10001";	-- SRA
95constant	sll_operation: 			std_logic_vector(4 downto 0)	:= "10010";	-- SLL
96constant	srl_operation:	 		std_logic_vector(4 downto 0)	:= "10011";	-- SRL
97constant	bit_operation:			std_logic_vector(4 downto 0)	:= "10100";	-- BIT
98constant	res_operation: 			std_logic_vector(4 downto 0)	:= "10101";	-- RES
99constant	set_operation:			std_logic_vector(4 downto 0)	:= "10110";	-- SET
100constant	in16_operation:			std_logic_vector(4 downto 0)	:= "10111";	-- in r, (c)
101constant	rld_operation:			std_logic_vector(4 downto 0)	:= "11000";	-- RLD
102constant	rrd_operation:			std_logic_vector(4 downto 0)	:= "11001";	-- RRD
103constant	blockterm16_operation:	std_logic_vector(4 downto 0)	:= "11010";	-- block instruction
104																				-- termination:
105																				-- P/V = 0 when
106																				-- BC = 0
107
108-- ALU operation flags masks - the ones that change are listed, others are masked out
109constant	alu_mask:				std_logic_vector(7 downto 0)	:= (	carry_bit => '1',
110																			add_sub_bit => '1',
111																			parity_overflow_bit => '1',
112																			half_carry_bit => '1',
113																			zero_bit => '1',
114																			sign_bit => '1',
115																			others => '0'
116																			);
117
118-- Block operation load masks
119constant	block_load_mask:		std_logic_vector(7 downto 0)	:= (	add_sub_bit => '1',
120																			parity_overflow_bit => '1',
121																			half_carry_bit => '1',
122																			others => '0'
123																			);
124
125constant	block_compare_mask1:	std_logic_vector(7 downto 0)	:= (	add_sub_bit => '1',
126																			half_carry_bit => '1',
127																			zero_bit => '1',
128																			sign_bit => '1',
129																			others => '0'
130																			);
131
132constant	block_compare_mask2:	std_logic_vector(7 downto 0)	:= (	parity_overflow_bit => '1',
133																			others => '0'
134																			);
135
136constant	block_io_mask:			std_logic_vector(7 downto 0)	:= (	add_sub_bit => '1',
137																			zero_bit => '1',
138																			others => '0'
139																			);
140
141-- bit masks for bit oriented instructions
142constant	bit7mask:	std_logic_vector(7 downto 0)	:= (7 => '1', others => '0');
143constant	bit6mask:	std_logic_vector(7 downto 0)	:= (6 => '1', others => '0');
144constant	bit5mask:	std_logic_vector(7 downto 0)	:= (5 => '1', others => '0');
145constant	bit4mask:	std_logic_vector(7 downto 0)	:= (4 => '1', others => '0');
146constant	bit3mask:	std_logic_vector(7 downto 0)	:= (3 => '1', others => '0');
147constant	bit2mask:	std_logic_vector(7 downto 0)	:= (2 => '1', others => '0');
148constant	bit1mask:	std_logic_vector(7 downto 0)	:= (1 => '1', others => '0');
149constant	bit0mask:	std_logic_vector(7 downto 0)	:= (0 => '1', others => '0');
150
151-- address bus selector
152constant	address_bus_source_BC:			std_logic_vector(3 downto 0)	:= x"0";
153constant	address_bus_source_DE:			std_logic_vector(3 downto 0)	:= x"1";
154constant	address_bus_source_HL:			std_logic_vector(3 downto 0)	:= x"2";
155constant	address_bus_source_SP:			std_logic_vector(3 downto 0)	:= x"3";
156constant	address_bus_source_PC:			std_logic_vector(3 downto 0)	:= x"4";
157constant	address_bus_source_operand:		std_logic_vector(3 downto 0)	:= x"5";
158constant	address_bus_source_operand1:	std_logic_vector(3 downto 0)	:= x"6";
159constant	address_bus_source_port8:		std_logic_vector(3 downto 0)	:= x"7";
160constant	address_bus_source_index:		std_logic_vector(3 downto 0)	:= x"8";
161
162-- program counter selector
163constant	pc_source_next:					std_logic_vector(3 downto 0)	:= x"0";	-- PC + 1
164constant	pc_source_operand:				std_logic_vector(3 downto 0)	:= x"1";	-- operand
165constant	pc_source_HL:					std_logic_vector(3 downto 0)	:= x"2";	-- PCHL
166constant	pc_source_return:				std_logic_vector(3 downto 0)	:= x"3";	-- return
167																						-- address
168constant	pc_source_next_next:			std_logic_vector(3 downto 0)	:= x"4";	-- PC + 2
169constant	pc_source_rst:					std_logic_vector(3 downto 0)	:= x"5";	-- RST nn
170constant	pc_source_index_register:		std_logic_vector(3 downto 0)	:= x"6";	-- PCIX and PCIY
171constant	pc_source_jr:					std_logic_vector(3 downto 0)	:= x"7";	-- JR offset
172constant	pc_source_block_repeat:			std_logic_vector(3 downto 0)	:= x"8";	-- for
173																						-- interrupted
174																						-- block repeats
175constant	pc_source_reset:				std_logic_vector(3 downto 0)	:= x"f";	-- sets PC
176																						-- vector
177																						-- after reset
178
179-- initial program counter.  Zilog spec says it is always zero, but often autojump hardware is
180-- implemented to change this.  I have the luxury of specifying the initial program counter as I see
181-- fit.
182constant	PC_start_address:				std_logic_vector(15 downto 0)	:= x"0000";
183
184-- SP source mux input definitins
185constant	SPsource_databus:				std_logic_vector(1 downto 0)	:= "00";	-- select
186																						-- databus
187constant	SPsource_increment:				std_logic_vector(1 downto 0)	:= "01";	-- select SP + 1
188constant	SPsource_decrement:				std_logic_vector(1 downto 0)	:= "10";	-- select SP - 1
189
190-- data output mux selectors
191constant	data_out_selector_databus:			std_logic_vector(2 downto 0)	:= "000";	-- select
192																							-- databus
193constant	data_out_selector_H:				std_logic_vector(2 downto 0)	:= "001";	-- select
194																							-- temporary
195																							-- register
196																							-- for
197																							-- register
198																							-- H
199constant	data_out_selector_L:				std_logic_vector(2 downto 0)	:= "010";	-- select
200																							-- temporary
201																							-- register
202																							-- for
203																							-- register
204																							-- L
205constant	data_out_selector_indexhigh:		std_logic_vector(2 downto 0)	:= "011";	-- select
206																							-- temporary
207																							-- register
208																							-- for
209																							-- register
210																							-- IXhigh
211constant	data_out_selector_indexlow:			std_logic_vector(2 downto 0)	:= "100";	-- select
212																							-- temporary
213																							-- register
214																							-- for
215																							-- register
216																							-- IXlow
217constant	data_out_selector_rrd_rld_output:	std_logic_vector(2 downto 0)	:= "101";	-- select
218																							-- secondary
219																							-- ALU
220																							-- output
221																							-- (RLD and
222																							-- RRD)
223
224-- select among return address, flags, or interrupt vector register to go through the ALU.
225constant	selectRetAddr:					std_logic_vector(1 downto 0)	:= "00";	-- select return
226																						-- address
227constant	selectFlags:					std_logic_vector(1 downto 0)	:= "01";	-- select flags
228constant	selectInterruptVector:			std_logic_vector(1 downto 0)	:= "10";	-- select
229																						-- interrupt
230																						-- vector
231																						-- register
232
233-- operand register selection
234constant	operandSelectLow:				std_logic	:= '0';	-- selects operand register low byte
235constant	operandSelectHigh:				std_logic	:= '1';	-- selects operand register bigh byte
236
237-- assertion and deassertion of control lines
238constant	assert_m1:						std_logic	:= '1';
239constant	deassert_m1:					std_logic	:= '0';
240constant	assert_write:					std_logic	:= '1';
241constant	deassert_write:					std_logic	:= '0';
242constant	assert_read:					std_logic	:= '1';
243constant	deassert_read:					std_logic	:= '0';
244constant	assert_iorq:					std_logic	:= '1';
245constant	deassert_iorq:					std_logic	:= '0';
246constant	assert_mreq:					std_logic	:= '1';
247constant	deassert_mreq:					std_logic	:= '0';
248
249-- Index register selection
250constant	SelectIndexIX:					std_logic	:= '0';
251constant	SelectIndexIY:					std_logic	:= '1';
252
253-- Return address byte selection
254constant	RetAddrLow:						std_logic	:= '0';
255constant	RetAddrHigh:					std_logic	:= '1';
256
257-- Enable and disable writing to instruction register
258constant	disableOpcodeWrite:				std_logic	:= '0';
259constant	enableOpcodeWrite:	   			std_logic	:= '1';
260
261-- Enable and disable XCHG hardware
262constant	disableXCHG:					std_logic	:= '0';
263constant	enableXCHG:			   			std_logic	:= '1';
264
265-- For master and slave control of the address, data and control busses
266constant	masterControl:					std_logic	:= '1';
267constant	slaveControl:					std_logic	:= '0';
268
269constant	deassert_halted:				std_logic	:= '0';
270constant	assert_halted:					std_logic	:= '1';
271
272-- For control of source of ALU operation
273constant	selectVHDL_ALU_operation:		std_logic	:= '0';
274constant	selectOpcode_ALU_operation:		std_logic	:= '1';
275
276-- for source of primary and secondary ALU operand registers
277constant	selectOpcodeRegister:			std_logic	:= '0';
278constant	selectVHDLRegister:				std_logic	:= '1';
279
280-- for register saving
281constant	save:							std_logic	:= '1';
282constant	DontSave:						std_logic	:= '0';
283
284-- for choosing source of flags data
285constant	ALUflags:						std_logic	:= '0';
286constant	POPflags:						std_logic	:= '1';
287
288-- for general clock enable and disable
289constant	clockEnable:					std_logic	:= '1';
290constant	clockDisable:					std_logic	:= '0';
291
292-- for invalid instruction detector
293constant	safe:							std_logic	:= '0';
294constant	fail:							std_logic	:= '1';
295
296-- for interrupt modes
297constant	IM_0:							std_logic_vector(1 downto 0)	:= "00";
298constant	IM_1:							std_logic_vector(1 downto 0)	:= "01";
299constant	IM_2:							std_logic_vector(1 downto 0)	:= "10";
300
301constant	width_is_8:						positive := 8;
302
303-- State numbers.  Done this way so state numbers can be stored and used as a return address
304
305-- common to all opcodes
306
307
308constant	initialise:					std_logic_vector(11 downto 0)	:= x"000";	-- initialise
309																					-- processor,
310																	 				-- enters on
311																	 				-- rising edge of
312																	 				-- clk_out
313constant	initialise1:				std_logic_vector(11 downto 0)	:= x"001";	-- second
314																					-- initialisation
315																	 				-- state
316constant	initialise2:				std_logic_vector(11 downto 0)	:= x"002";	-- third
317																					-- initialisation
318																	 				-- state
319constant	initialise3:				std_logic_vector(11 downto 0)	:= x"003";	-- fourth
320																					-- initialisation
321																	 				-- state
322constant	opcode:						std_logic_vector(11 downto 0)	:= x"004";	-- assert pc address
323																					-- drivers and
324																					-- m1n = '0'
325																					-- for 1st opcode
326																					-- byte, rising edge
327																					-- of clock, done
328																					-- in last state of
329																					-- previous
330																					-- instruction
331constant	opcode_mreq:				std_logic_vector(11 downto 0)	:= x"005";	-- assert
332																					-- mreqn = '0' and
333																					-- rdn = '0' on
334																					-- falling edge of
335																					-- clock
336constant	opcode_latch:				std_logic_vector(11 downto 0)	:= x"006";	-- latch opcode byte
337																					-- on next rising
338																					-- edge of clock
339																					-- with waitn = '1',
340																					-- rising edge of
341																					-- clock
342constant	decode_opcode:				std_logic_vector(11 downto 0)	:= x"007";	-- decode first
343																					-- opcode
344constant	invalid:					std_logic_vector(11 downto 0)	:= x"008";	-- state name for
345																					-- invalid return
346																					-- state and illegal
347																					-- instruction
348
349-- states for BUSRQ handling
350constant	busrq:						std_logic_vector(11 downto 0)	:= x"009";
351
352-- New PC state for use with jr, jp, ret, call, rst
353constant	NewPC:						std_logic_vector(11 downto 0)	:= x"00f";
354
355-- opcodes in order presented by z80.info/decoding.  Number of states (initially) conforms
356-- to number of clock cycles as advertised in the Z80 data sheet.  States are added because
357-- I process information on both positive and negative transitions of the clock.  These
358-- will be removed if they are not needed. Memory and port I/O operations are always
359-- initiated at the positive going edge of the clock.  Instructions that do not appear here
360-- are processed entirely during the decoding phase of operation.
361
362-- NOP states, 4 clock cycles, all required for timing loops, 1 m1 cycle
363constant	nop4:						std_logic_vector(11 downto 0)	:= x"010";	-- instruction
364																					-- origin + 3 rising
365																					-- edges
366constant	nop5:						std_logic_vector(11 downto 0)	:= x"011";	-- instruction
367																					-- origin + 4 rising
368																					-- edges
369
370-- DJNZ, 8/13 cycles (met, not met), 1 m1 cycle
371constant	djnz4:						std_logic_vector(11 downto 0)	:= x"030";
372
373-- JR, 12 cycles, 1 m1 cycle
374constant	jr4:						std_logic_vector(11 downto 0)	:= x"040";
375constant	jr5:						std_logic_vector(11 downto 0)	:= x"041";
376constant	jr6:						std_logic_vector(11 downto 0)	:= x"042";
377constant	jr7:						std_logic_vector(11 downto 0)	:= x"043";
378
379-- JR conditional, 12/7 cycles (met/not met), 1 m1 cycle
380-- need one state to test condition, transfer control to jr code
381-- Number of cycles = one or two more than jr
382constant	jrcc4:						std_logic_vector(11 downto 0)	:= x"050";
383constant	jrcc5:						std_logic_vector(11 downto 0)	:= x"051";
384
385-- LD rp, immediate, 10 cycles, 1 m1 cycle
386constant	ldrpi4:						std_logic_vector(11 downto 0)	:= x"060";
387constant	ldrpi5:						std_logic_vector(11 downto 0)	:= x"061";
388
389-- ADD HL, rp, 11 clock cycles, 1 m1 cycle
390constant	addhlrp4:					std_logic_vector(11 downto 0)	:= x"070";
391constant	addhlrp5:					std_logic_vector(11 downto 0)	:= x"071";
392
393-- LDAX rp, 7 cycles, 1 m1 cycle
394constant	ldax4:						std_logic_vector(11 downto 0)	:= x"080";
395constant	ldax5:						std_logic_vector(11 downto 0)	:= x"081";
396
397-- STAX rp, 7 cycles, 1 m1 cycle
398constant	stax4:						std_logic_vector(11 downto 0)	:= x"090";
399constant	stax5:						std_logic_vector(11 downto 0)	:= x"091";
400
401-- LDA nn, 13 cycles, 1 m1 cycle
402constant	lda4:						std_logic_vector(11 downto 0)	:= x"0a0";
403constant	lda5:						std_logic_vector(11 downto 0)	:= x"0a1";
404constant	lda6:						std_logic_vector(11 downto 0)	:= x"0a2";
405constant	lda7:						std_logic_vector(11 downto 0)	:= x"0a3";
406
407-- STA nn, 13 cycles, 1 m1 cycle
408constant	sta4:						std_logic_vector(11 downto 0)	:= x"0b0";
409constant	sta5:						std_logic_vector(11 downto 0)	:= x"0b1";
410
411
412-- LHLD (nn), 16 cycles, 1 m1 cycle
413constant	ldhl4:						std_logic_vector(11 downto 0)	:= x"0c0";
414constant	ldhl5:						std_logic_vector(11 downto 0)	:= x"0c1";
415constant	ldhl6:						std_logic_vector(11 downto 0)	:= x"0c2";
416constant	ldhl7:						std_logic_vector(11 downto 0)	:= x"0c3";
417constant	ldhl8:						std_logic_vector(11 downto 0)	:= x"0c4";
418
419-- SHLD (nn), 16 cycles, 1 m1 cycle
420constant	sthl4:						std_logic_vector(11 downto 0)	:= x"0d0";
421constant	sthl5:						std_logic_vector(11 downto 0)	:= x"0d1";
422constant	sthl6:						std_logic_vector(11 downto 0)	:= x"0d2";
423constant	sthl7:						std_logic_vector(11 downto 0)	:= x"0d3";
424
425-- 16 bit increment/decrement, 6 cycles, 1 m1 cycle
426constant	incdec16_4:					std_logic_vector(11 downto 0)	:= x"0e0";
427constant	incdec16_5:					std_logic_vector(11 downto 0)	:= x"0e1";
428constant	incdec16_6:					std_logic_vector(11 downto 0)	:= x"0e2";
429constant	incdec16_7:					std_logic_vector(11 downto 0)	:= x"0e3";
430
431-- 8 bit register/memory increment/decrement, 11 cycles, 1 m1 cycle
432constant	incdec8_4:					std_logic_vector(11 downto 0)	:= x"0f0";
433
434-- 8 bit load immediate, 7 cycles, 1 m1 cycle
435constant	ldi4:						std_logic_vector(11 downto 0)	:= x"100";
436
437-- DAA, 4 cycles, 1 m1 cycle
438constant	daa4:						std_logic_vector(11 downto 0)	:= x"110";
439constant	daa5:						std_logic_vector(11 downto 0)	:= x"111";
440constant	daa6:						std_logic_vector(11 downto 0)	:= x"112";
441constant	daa7:						std_logic_vector(11 downto 0)	:= x"113";
442
443-- SCF/CCF, 4 cycles, 1 m1 cycle
444-- main processing done at instruction decoder stage
445constant	scf_ccf_save:				std_logic_vector(11 downto 0)	:= x"120";
446
447-- inter-register 8 bit loading, 4 cycles, 1 m1 cycle
448constant	irld4:						std_logic_vector(11 downto 0)	:= x"130";
449constant	irld5:						std_logic_vector(11 downto 0)	:= x"131";
450
451-- HALT, 4 cycles, 1 m1 cycle, may trim this to three
452-- cycles initially plus one cycle per instruction thereafter
453constant	halt4:						std_logic_vector(11 downto 0)	:= x"140";
454constant	halt5:						std_logic_vector(11 downto 0)	:= x"141";
455constant	halt6:						std_logic_vector(11 downto 0)	:= x"142";
456constant	halt7:						std_logic_vector(11 downto 0)	:= x"143";
457
458-- alu operations on registers, 4 cycles, 1 m1 cycle
459constant	alu4:						std_logic_vector(11 downto 0)	:= x"150";
460
461-- POP, 10 cycles, 1 m1 cycle
462constant	pop4:						std_logic_vector(11 downto 0)	:= x"160";
463constant	pop5:						std_logic_vector(11 downto 0)	:= x"161";
464constant	pop6:						std_logic_vector(11 downto 0)	:= x"162";
465constant	pop7:						std_logic_vector(11 downto 0)	:= x"163";
466constant	pop8:						std_logic_vector(11 downto 0)	:= x"164";
467
468-- RET unconditional, 10 cycles, 1 m1 cycle
469constant	ret4:						std_logic_vector(11 downto 0)	:= x"170";
470constant	ret5:						std_logic_vector(11 downto 0)	:= x"171";
471constant	ret6:						std_logic_vector(11 downto 0)	:= x"172";
472constant	ret7:						std_logic_vector(11 downto 0)	:= x"173";
473constant	ret8:						std_logic_vector(11 downto 0)	:= x"174";
474constant	ret9:						std_logic_vector(11 downto 0)	:= x"175";
475
476-- JP HL, 4 cycles,1 m1 cycle
477constant	jphl4:						std_logic_vector(11 downto 0)	:= x"180";
478
479-- LD SP, HL, 6 cycles, 1 m1 cycle
480constant	sphl4:						std_logic_vector(11 downto 0)	:= x"190";
481
482-- JP conditional, 10 cycles met or not, 1 m1 cycle
483-- use one state to determine if ret is to be executed, then transfer to JP unconditional if so.
484constant	jpcc4:						std_logic_vector(11 downto 0)	:= x"1a0";
485constant	jpcc5:						std_logic_vector(11 downto 0)	:= x"1a1";
486
487-- JP unconditional, 10 cycles, 1 m1 cycle
488constant	jp4:						std_logic_vector(11 downto 0)	:= x"1b0";
489constant	jp5:						std_logic_vector(11 downto 0)	:= x"1b1";
490constant	jp6:						std_logic_vector(11 downto 0)	:= x"1b2";
491
492-- CB prefix, must obtain next instruction byte
493constant	cb4:						std_logic_vector(11 downto 0)	:= x"1c0";
494constant	cb5:						std_logic_vector(11 downto 0)	:= x"1c1";
495
496-- save results from CB prefixed opcodes other than BIT, SET, and RES
497constant	bitsave:					std_logic_vector(11 downto 0)	:= x"1e0";
498
499-- common state for save and load 16 bit registers with ED prefix
500constant	rp16io:						std_logic_vector(11 downto 0)	:= x"1f0";
501
502-- BIT
503constant	bit6:						std_logic_vector(11 downto 0)	:= x"200";
504constant	bit7:						std_logic_vector(11 downto 0)	:= x"201";
505
506-- RES
507constant	res6:						std_logic_vector(11 downto 0)	:= x"210";
508
509-- SET
510constant	set6:						std_logic_vector(11 downto 0)	:= x"220";
511
512-- end of CB prefixed opcodes
513
514-- 8 bit output of accumulator to 8 bit port address, 11 cycles, 1 m1 cycle
515constant	out4:						std_logic_vector(11 downto 0)	:= x"230";
516constant	out5:						std_logic_vector(11 downto 0)	:= x"231";
517constant	out6:						std_logic_vector(11 downto 0)	:= x"232";
518constant	out7:						std_logic_vector(11 downto 0)	:= x"233";
519constant	out8:						std_logic_vector(11 downto 0)	:= x"234";
520
521-- 8 bit input of accumulator from 8 bit port address, 11 cycles, 1 m1 cycle
522constant	in4:						std_logic_vector(11 downto 0)	:= x"240";
523constant	in5:						std_logic_vector(11 downto 0)	:= x"241";
524constant	in6:						std_logic_vector(11 downto 0)	:= x"242";
525constant	in7:						std_logic_vector(11 downto 0)	:= x"243";
526
527-- EX (SP), HL, 19 cycles, 1 m1 cycle
528constant	xthl4:						std_logic_vector(11 downto 0)	:= x"250";
529constant	xthl5:						std_logic_vector(11 downto 0)	:= x"251";
530constant	xthl6:						std_logic_vector(11 downto 0)	:= x"252";
531constant	xthl7:						std_logic_vector(11 downto 0)	:= x"253";
532constant	xthl8:						std_logic_vector(11 downto 0)	:= x"254";
533constant	xthl9:						std_logic_vector(11 downto 0)	:= x"255";
534constant	xthl10:						std_logic_vector(11 downto 0)	:= x"256";
535
536-- DI, 4 cycles, 1 m1 cycle
537constant	di4:						std_logic_vector(11 downto 0)	:= x"270";
538constant	di5:						std_logic_vector(11 downto 0)	:= x"271";
539constant	di6:						std_logic_vector(11 downto 0)	:= x"272";
540constant	di7:						std_logic_vector(11 downto 0)	:= x"273";
541
542-- EI, 4 cycles, 1 m1 cycle
543constant	ei4:						std_logic_vector(11 downto 0)	:= x"280";
544constant	ei5:						std_logic_vector(11 downto 0)	:= x"281";
545constant	ei6:						std_logic_vector(11 downto 0)	:= x"282";
546constant	ei7:						std_logic_vector(11 downto 0)	:= x"283";
547
548-- PUSH, 10 cycles, 1 m1 cycle
549constant	push4:						std_logic_vector(11 downto 0)	:= x"2a0";
550constant	push5:						std_logic_vector(11 downto 0)	:= x"2a1";
551constant	push6:						std_logic_vector(11 downto 0)	:= x"2a2";
552constant	push7:						std_logic_vector(11 downto 0)	:= x"2a3";
553
554-- CALL unconditional, 17 clock cycles, 1 m1 cycle
555constant	call4:						std_logic_vector(11 downto 0)	:= x"2b0";
556constant	call5:						std_logic_vector(11 downto 0)	:= x"2b1";
557constant	call6:						std_logic_vector(11 downto 0)	:= x"2b2";
558constant	call7:						std_logic_vector(11 downto 0)	:= x"2b3";
559constant	call8:						std_logic_vector(11 downto 0)	:= x"2b4";
560
561-- end of DD prefixed opcodes
562
563-- ED prefix, must obtain next instruction byte
564constant	ed4:						std_logic_vector(11 downto 0)	:= x"2c0";
565constant	ed5:						std_logic_vector(11 downto 0)	:= x"2c1";
566constant	ed6:						std_logic_vector(11 downto 0)	:= x"2c2";
567constant	ed7:						std_logic_vector(11 downto 0)	:= x"2c3";
568constant	ed8:						std_logic_vector(11 downto 0)	:= x"2c4";
569constant	ed9:						std_logic_vector(11 downto 0)	:= x"2c5";
570constant	ed10:						std_logic_vector(11 downto 0)	:= x"2c6";
571
572-- 8 bit input to register from a 16 bit port address, 12 cycles, 1 m1 cycle
573constant	in16_5:						std_logic_vector(11 downto 0)	:= x"2d0";
574constant	in16_6:						std_logic_vector(11 downto 0)	:= x"2d1";
575
576-- 8 bit output to register from a 16 bit port address, 12 cycles, 1 m1 cycle
577constant	out16_5:					std_logic_vector(11 downto 0)	:= x"2e0";
578constant	out16_6:					std_logic_vector(11 downto 0)	:= x"2e1";
579
580-- 16 bit ADC
581constant	adc_sbc_16_5:				std_logic_vector(11 downto 0)	:= x"2f0";
582
583-- store register pair to immediate address
584constant	strp16_5:					std_logic_vector(11 downto 0)	:= x"300";
585constant	strp16_6:					std_logic_vector(11 downto 0)	:= x"301";
586
587-- load register pair from immediate address
588constant	ldrp16_5:					std_logic_vector(11 downto 0)	:= x"310";
589constant	ldrp16_6:					std_logic_vector(11 downto 0)	:= x"311";
590constant	ldrp16_7:					std_logic_vector(11 downto 0)	:= x"312";
591
592-- NEG
593constant	neg6:						std_logic_vector(11 downto 0)	:= x"320";
594
595-- RETN
596constant	retn6:						std_logic_vector(11 downto 0)	:= x"330";
597constant	retn7:						std_logic_vector(11 downto 0)	:= x"331";
598constant	retn8:						std_logic_vector(11 downto 0)	:= x"332";
599constant	retn9:						std_logic_vector(11 downto 0)	:= x"333";
600constant	retn10:						std_logic_vector(11 downto 0)	:= x"334";
601constant	retn11:						std_logic_vector(11 downto 0)	:= x"335";
602constant	retn12:						std_logic_vector(11 downto 0)	:= x"336";
603constant	retn13:						std_logic_vector(11 downto 0)	:= x"337";
604constant	retn14:						std_logic_vector(11 downto 0)	:= x"338";
605constant	retn15:						std_logic_vector(11 downto 0)	:= x"339";
606constant	retn16:						std_logic_vector(11 downto 0)	:= x"33a";
607constant	retn17:						std_logic_vector(11 downto 0)	:= x"33b";
608constant	retn18:						std_logic_vector(11 downto 0)	:= x"33c";
609constant	retn19:						std_logic_vector(11 downto 0)	:= x"33d";
610constant	retn20:						std_logic_vector(11 downto 0)	:= x"33e";
611constant	retn21:						std_logic_vector(11 downto 0)	:= x"33f";
612constant	retn22:						std_logic_vector(11 downto 0)	:= x"340";
613constant	retn23:						std_logic_vector(11 downto 0)	:= x"342";
614constant	retn24:						std_logic_vector(11 downto 0)	:= x"343";
615constant	retn25:						std_logic_vector(11 downto 0)	:= x"344";
616
617-- RETI
618constant	reti6:						std_logic_vector(11 downto 0)	:= x"350";
619constant	reti7:						std_logic_vector(11 downto 0)	:= x"351";
620constant	reti8:						std_logic_vector(11 downto 0)	:= x"352";
621constant	reti9:						std_logic_vector(11 downto 0)	:= x"353";
622constant	reti10:						std_logic_vector(11 downto 0)	:= x"354";
623constant	reti11:						std_logic_vector(11 downto 0)	:= x"355";
624constant	reti12:						std_logic_vector(11 downto 0)	:= x"356";
625constant	reti13:						std_logic_vector(11 downto 0)	:= x"357";
626constant	reti14:						std_logic_vector(11 downto 0)	:= x"358";
627constant	reti15:						std_logic_vector(11 downto 0)	:= x"359";
628constant	reti16:						std_logic_vector(11 downto 0)	:= x"35a";
629constant	reti17:						std_logic_vector(11 downto 0)	:= x"35b";
630constant	reti18:						std_logic_vector(11 downto 0)	:= x"35c";
631constant	reti19:						std_logic_vector(11 downto 0)	:= x"35d";
632constant	reti20:						std_logic_vector(11 downto 0)	:= x"35e";
633constant	reti21:						std_logic_vector(11 downto 0)	:= x"35f";
634constant	reti22:						std_logic_vector(11 downto 0)	:= x"360";
635constant	reti23:						std_logic_vector(11 downto 0)	:= x"361";
636constant	reti24:						std_logic_vector(11 downto 0)	:= x"362";
637constant	reti25:						std_logic_vector(11 downto 0)	:= x"363";
638
639-- IM n
640constant	im0_6:						std_logic_vector(11 downto 0)	:= x"370";
641constant	im0_7:						std_logic_vector(11 downto 0)	:= x"371";
642constant	im0_8:						std_logic_vector(11 downto 0)	:= x"372";
643constant	im0_9:						std_logic_vector(11 downto 0)	:= x"373";
644constant	im0_10:						std_logic_vector(11 downto 0)	:= x"374";
645constant	im0_11:						std_logic_vector(11 downto 0)	:= x"375";
646constant	im0_12:						std_logic_vector(11 downto 0)	:= x"376";
647constant	im0_13:						std_logic_vector(11 downto 0)	:= x"377";
648
649constant	im1_6:						std_logic_vector(11 downto 0)	:= x"380";
650constant	im1_7:						std_logic_vector(11 downto 0)	:= x"381";
651constant	im1_8:						std_logic_vector(11 downto 0)	:= x"382";
652constant	im1_9:						std_logic_vector(11 downto 0)	:= x"383";
653constant	im1_10:						std_logic_vector(11 downto 0)	:= x"384";
654constant	im1_11:						std_logic_vector(11 downto 0)	:= x"385";
655constant	im1_12:						std_logic_vector(11 downto 0)	:= x"386";
656constant	im1_13:						std_logic_vector(11 downto 0)	:= x"387";
657
658constant	im2_6:						std_logic_vector(11 downto 0)	:= x"390";
659constant	im2_7:						std_logic_vector(11 downto 0)	:= x"391";
660constant	im2_8:						std_logic_vector(11 downto 0)	:= x"392";
661constant	im2_9:						std_logic_vector(11 downto 0)	:= x"393";
662constant	im2_10:						std_logic_vector(11 downto 0)	:= x"394";
663constant	im2_11:						std_logic_vector(11 downto 0)	:= x"395";
664constant	im2_12:						std_logic_vector(11 downto 0)	:= x"396";
665constant	im2_13:						std_logic_vector(11 downto 0)	:= x"397";
666
667-- LD I, A
668constant	ldia5:						std_logic_vector(11 downto 0)	:= x"3a0";
669constant	ldia6:						std_logic_vector(11 downto 0)	:= x"3a1";
670constant	ldia7:						std_logic_vector(11 downto 0)	:= x"3a2";
671constant	ldia8:						std_logic_vector(11 downto 0)	:= x"3a3";
672constant	ldia9:						std_logic_vector(11 downto 0)	:= x"3a4";
673constant	ldia10:						std_logic_vector(11 downto 0)	:= x"3a5";
674constant	ldia11:						std_logic_vector(11 downto 0)	:= x"3a6";
675constant	ldia12:						std_logic_vector(11 downto 0)	:= x"3a7";
676constant	ldia13:						std_logic_vector(11 downto 0)	:= x"3a8";
677constant	ldia14:						std_logic_vector(11 downto 0)	:= x"3a9";
678
679-- LD R, A, ignore this instruction
680
681-- LD A, I
682constant	ldai5:						std_logic_vector(11 downto 0)	:= x"3b0";
683constant	ldai6:						std_logic_vector(11 downto 0)	:= x"3b1";
684constant	ldai7:						std_logic_vector(11 downto 0)	:= x"3b2";
685constant	ldai8:						std_logic_vector(11 downto 0)	:= x"3b3";
686constant	ldai9:						std_logic_vector(11 downto 0)	:= x"3b4";
687constant	ldai10:						std_logic_vector(11 downto 0)	:= x"3b5";
688constant	ldai11:						std_logic_vector(11 downto 0)	:= x"3b6";
689constant	ldai12:						std_logic_vector(11 downto 0)	:= x"3b7";
690constant	ldai13:						std_logic_vector(11 downto 0)	:= x"3b8";
691constant	ldai14:						std_logic_vector(11 downto 0)	:= x"3b9";
692
693-- LD A, R, ignore this instruction
694
695-- RRD and RLD
696constant	rrd_rld5:					std_logic_vector(11 downto 0)	:= x"3c0";
697
698-- Block instructions
699
700-- LDI
701constant	bldi5:						std_logic_vector(11 downto 0)	:= x"3d0";
702constant	bldi6:						std_logic_vector(11 downto 0)	:= x"3d1";
703constant	bldi7:						std_logic_vector(11 downto 0)	:= x"3d2";
704constant	bldi8:						std_logic_vector(11 downto 0)	:= x"3d3";
705constant	bldi9:						std_logic_vector(11 downto 0)	:= x"3d4";
706constant	bldi10:						std_logic_vector(11 downto 0)	:= x"3d5";
707constant	bldi11:						std_logic_vector(11 downto 0)	:= x"3d6";
708constant	bldi12:						std_logic_vector(11 downto 0)	:= x"3d7";
709constant	bldi13:						std_logic_vector(11 downto 0)	:= x"3d8";
710constant	bldi14:						std_logic_vector(11 downto 0)	:= x"3d9";
711
712-- CPI
713constant	bcpi5:						std_logic_vector(11 downto 0)	:= x"3e0";
714constant	bcpi6:						std_logic_vector(11 downto 0)	:= x"3e1";
715constant	bcpi7:						std_logic_vector(11 downto 0)	:= x"3e2";
716constant	bcpi8:						std_logic_vector(11 downto 0)	:= x"3e3";
717constant	bcpi9:						std_logic_vector(11 downto 0)	:= x"3e4";
718constant	bcpi10:						std_logic_vector(11 downto 0)	:= x"3e5";
719constant	bcpi11:						std_logic_vector(11 downto 0)	:= x"3e6";
720
721-- INI
722constant	bini5:						std_logic_vector(11 downto 0)	:= x"3f0";
723constant	bini6:						std_logic_vector(11 downto 0)	:= x"3f1";
724constant	bini7:						std_logic_vector(11 downto 0)	:= x"3f2";
725constant	bini8:						std_logic_vector(11 downto 0)	:= x"3f3";
726constant	bini9:						std_logic_vector(11 downto 0)	:= x"3f4";
727constant	bini10:						std_logic_vector(11 downto 0)	:= x"3f5";
728constant	bini11:						std_logic_vector(11 downto 0)	:= x"3f6";
729
730-- OUTI
731constant	bouti5:						std_logic_vector(11 downto 0)	:= x"400";
732constant	bouti6:						std_logic_vector(11 downto 0)	:= x"401";
733constant	bouti7:						std_logic_vector(11 downto 0)	:= x"402";
734constant	bouti8:						std_logic_vector(11 downto 0)	:= x"403";
735constant	bouti9:						std_logic_vector(11 downto 0)	:= x"404";
736constant	bouti10:					std_logic_vector(11 downto 0)	:= x"405";
737constant	bouti11:					std_logic_vector(11 downto 0)	:= x"406";
738constant	bouti12:					std_logic_vector(11 downto 0)	:= x"407";
739
740-- LDD
741constant	bldd5:						std_logic_vector(11 downto 0)	:= x"410";
742constant	bldd6:						std_logic_vector(11 downto 0)	:= x"411";
743constant	bldd7:						std_logic_vector(11 downto 0)	:= x"412";
744constant	bldd8:						std_logic_vector(11 downto 0)	:= x"413";
745constant	bldd9:						std_logic_vector(11 downto 0)	:= x"414";
746constant	bldd10:						std_logic_vector(11 downto 0)	:= x"415";
747constant	bldd11:						std_logic_vector(11 downto 0)	:= x"416";
748constant	bldd12:						std_logic_vector(11 downto 0)	:= x"417";
749constant	bldd13:						std_logic_vector(11 downto 0)	:= x"418";
750
751-- CPD
752constant	bcpd5:						std_logic_vector(11 downto 0)	:= x"420";
753constant	bcpd6:						std_logic_vector(11 downto 0)	:= x"421";
754constant	bcpd7:						std_logic_vector(11 downto 0)	:= x"422";
755constant	bcpd8:						std_logic_vector(11 downto 0)	:= x"423";
756constant	bcpd9:						std_logic_vector(11 downto 0)	:= x"424";
757constant	bcpd10:						std_logic_vector(11 downto 0)	:= x"425";
758constant	bcpd11:						std_logic_vector(11 downto 0)	:= x"426";
759
760-- IND
761constant	bind5:						std_logic_vector(11 downto 0)	:= x"430";
762constant	bind6:						std_logic_vector(11 downto 0)	:= x"431";
763constant	bind7:						std_logic_vector(11 downto 0)	:= x"432";
764constant	bind8:						std_logic_vector(11 downto 0)	:= x"433";
765constant	bind9:						std_logic_vector(11 downto 0)	:= x"434";
766constant	bind10:						std_logic_vector(11 downto 0)	:= x"435";
767constant	bind11:						std_logic_vector(11 downto 0)	:= x"436";
768
769-- OUTD
770constant	boutd5:						std_logic_vector(11 downto 0)	:= x"440";
771constant	boutd6:						std_logic_vector(11 downto 0)	:= x"441";
772constant	boutd7:						std_logic_vector(11 downto 0)	:= x"442";
773constant	boutd8:						std_logic_vector(11 downto 0)	:= x"443";
774constant	boutd9:						std_logic_vector(11 downto 0)	:= x"444";
775constant	boutd10:					std_logic_vector(11 downto 0)	:= x"445";
776constant	boutd11:					std_logic_vector(11 downto 0)	:= x"446";
777
778-- LDIR
779constant	bldir5:						std_logic_vector(11 downto 0)	:= x"450";
780constant	bldir6:						std_logic_vector(11 downto 0)	:= x"451";
781--constant	bldir7:						std_logic_vector(11 downto 0)	:= x"452";
782--constant	bldir8:						std_logic_vector(11 downto 0)	:= x"453";
783--constant	bldir9:			  			std_logic_vector(11 downto 0)	:= x"454";
784--constant	bldir10:					std_logic_vector(11 downto 0)	:= x"455";
785--constant	bldir11:					std_logic_vector(11 downto 0)	:= x"456";
786--constant	bldir12:					std_logic_vector(11 downto 0)	:= x"457";
787--constant	bldir13:					std_logic_vector(11 downto 0)	:= x"458";
788--constant	bldir14:					std_logic_vector(11 downto 0)	:= x"459";
789--constant	bldir15:					std_logic_vector(11 downto 0)	:= x"45a";
790--constant	bldir16:					std_logic_vector(11 downto 0)	:= x"45b";
791--constant	bldir17:					std_logic_vector(11 downto 0)	:= x"45c";
792--constant	bldir18:					std_logic_vector(11 downto 0)	:= x"45d";
793--constant	bldir19:					std_logic_vector(11 downto 0)	:= x"45e";
794--constant	bldir20:					std_logic_vector(11 downto 0)	:= x"45f";
795--constant	bldir21:					std_logic_vector(11 downto 0)	:= x"460";
796--constant	bldir22:					std_logic_vector(11 downto 0)	:= x"461";
797--constant	bldir23:					std_logic_vector(11 downto 0)	:= x"462";
798--constant	bldir24:					std_logic_vector(11 downto 0)	:= x"463";
799--constant	bldir25:					std_logic_vector(11 downto 0)	:= x"464";
800--constant	bldir26:					std_logic_vector(11 downto 0)	:= x"465";
801--constant	bldir27:					std_logic_vector(11 downto 0)	:= x"466";
802--constant	bldir28:					std_logic_vector(11 downto 0)	:= x"467";
803--constant	bldir29:					std_logic_vector(11 downto 0)	:= x"468";
804--constant	bldir30:					std_logic_vector(11 downto 0)	:= x"469";
805--constant	bldir31:					std_logic_vector(11 downto 0)	:= x"46a";
806--constant	bldir32:					std_logic_vector(11 downto 0)	:= x"46b";
807--constant	bldir33:					std_logic_vector(11 downto 0)	:= x"46c";
808--constant	bldir34:					std_logic_vector(11 downto 0)	:= x"46d";
809--constant	bldir35:					std_logic_vector(11 downto 0)	:= x"46e";
810--constant	bldir36:					std_logic_vector(11 downto 0)	:= x"46f";
811--constant	bldir37:					std_logic_vector(11 downto 0)	:= x"470";
812--constant	bldir38:					std_logic_vector(11 downto 0)	:= x"471";
813
814-- CPIR
815constant	bcpir5:						std_logic_vector(11 downto 0)	:= x"480";
816constant	bcpir6:						std_logic_vector(11 downto 0)	:= x"481";
817--constant	bcpir7:						std_logic_vector(11 downto 0)	:= x"482";
818--constant	bcpir8:						std_logic_vector(11 downto 0)	:= x"483";
819--constant	bcpir9:						std_logic_vector(11 downto 0)	:= x"484";
820--constant	bcpir10:					std_logic_vector(11 downto 0)	:= x"485";
821--constant	bcpir11:					std_logic_vector(11 downto 0)	:= x"486";
822--constant	bcpir12:					std_logic_vector(11 downto 0)	:= x"487";
823--constant	bcpir13:					std_logic_vector(11 downto 0)	:= x"488";
824--constant	bcpir14:					std_logic_vector(11 downto 0)	:= x"489";
825--constant	bcpir15:					std_logic_vector(11 downto 0)	:= x"48a";
826--constant	bcpir16:					std_logic_vector(11 downto 0)	:= x"48b";
827--constant	bcpir17:					std_logic_vector(11 downto 0)	:= x"48c";
828--constant	bcpir18:					std_logic_vector(11 downto 0)	:= x"48d";
829--constant	bcpir19:					std_logic_vector(11 downto 0)	:= x"48e";
830--constant	bcpir20:					std_logic_vector(11 downto 0)	:= x"48f";
831--constant	bcpir21:					std_logic_vector(11 downto 0)	:= x"490";
832--constant	bcpir22:					std_logic_vector(11 downto 0)	:= x"491";
833--constant	bcpir23:					std_logic_vector(11 downto 0)	:= x"492";
834--constant	bcpir24:					std_logic_vector(11 downto 0)	:= x"493";
835--constant	bcpir25:					std_logic_vector(11 downto 0)	:= x"494";
836--constant	bcpir26:					std_logic_vector(11 downto 0)	:= x"495";
837--constant	bcpir27:					std_logic_vector(11 downto 0)	:= x"496";
838--constant	bcpir28:					std_logic_vector(11 downto 0)	:= x"497";
839--constant	bcpir29:					std_logic_vector(11 downto 0)	:= x"498";
840--constant	bcpir30:					std_logic_vector(11 downto 0)	:= x"499";
841--constant	bcpir31:					std_logic_vector(11 downto 0)	:= x"49a";
842--constant	bcpir32:					std_logic_vector(11 downto 0)	:= x"49b";
843--constant	bcpir33:					std_logic_vector(11 downto 0)	:= x"49c";
844--constant	bcpir34:					std_logic_vector(11 downto 0)	:= x"49d";
845--constant	bcpir35:					std_logic_vector(11 downto 0)	:= x"49e";
846--constant	bcpir36:					std_logic_vector(11 downto 0)	:= x"49f";
847--constant	bcpir37:					std_logic_vector(11 downto 0)	:= x"4a0";
848--constant	bcpir38:					std_logic_vector(11 downto 0)	:= x"4a1";
849
850-- INIR
851constant	binir5:						std_logic_vector(11 downto 0)	:= x"4b0";
852constant	binir6:						std_logic_vector(11 downto 0)	:= x"4b1";
853--constant	binir7:						std_logic_vector(11 downto 0)	:= x"4b2";
854--constant	binir8:						std_logic_vector(11 downto 0)	:= x"4b3";
855--constant	binir9:						std_logic_vector(11 downto 0)	:= x"4b4";
856--constant	binir10:					std_logic_vector(11 downto 0)	:= x"4b5";
857--constant	binir11:					std_logic_vector(11 downto 0)	:= x"4b6";
858--constant	binir12:					std_logic_vector(11 downto 0)	:= x"4b7";
859--constant	binir13:					std_logic_vector(11 downto 0)	:= x"4b8";
860--constant	binir14:					std_logic_vector(11 downto 0)	:= x"4b9";
861--constant	binir15:					std_logic_vector(11 downto 0)	:= x"4ba";
862--constant	binir16:					std_logic_vector(11 downto 0)	:= x"4bb";
863--constant	binir17:					std_logic_vector(11 downto 0)	:= x"4bc";
864--constant	binir18:					std_logic_vector(11 downto 0)	:= x"4bd";
865--constant	binir19:					std_logic_vector(11 downto 0)	:= x"4be";
866--constant	binir20:					std_logic_vector(11 downto 0)	:= x"4bf";
867--constant	binir21:					std_logic_vector(11 downto 0)	:= x"4c0";
868--constant	binir22:					std_logic_vector(11 downto 0)	:= x"4c1";
869--constant	binir23:					std_logic_vector(11 downto 0)	:= x"4c2";
870--constant	binir24:					std_logic_vector(11 downto 0)	:= x"4c3";
871--constant	binir25:					std_logic_vector(11 downto 0)	:= x"4c4";
872--constant	binir26:					std_logic_vector(11 downto 0)	:= x"4c5";
873--constant	binir27:					std_logic_vector(11 downto 0)	:= x"4c6";
874--constant	binir28:					std_logic_vector(11 downto 0)	:= x"4c7";
875--constant	binir29:					std_logic_vector(11 downto 0)	:= x"4c8";
876--constant	binir30:					std_logic_vector(11 downto 0)	:= x"4c9";
877--constant	binir31:					std_logic_vector(11 downto 0)	:= x"4ca";
878--constant	binir32:					std_logic_vector(11 downto 0)	:= x"4cb";
879--constant	binir33:					std_logic_vector(11 downto 0)	:= x"4cc";
880--constant	binir34:					std_logic_vector(11 downto 0)	:= x"4cd";
881--constant	binir35:					std_logic_vector(11 downto 0)	:= x"4ce";
882--constant	binir36:					std_logic_vector(11 downto 0)	:= x"4cf";
883--constant	binir37:					std_logic_vector(11 downto 0)	:= x"4d0";
884--constant	binir38:					std_logic_vector(11 downto 0)	:= x"4d1";
885
886-- OTIR
887constant	botir5:						std_logic_vector(11 downto 0)	:= x"4e0";
888constant	botir6:						std_logic_vector(11 downto 0)	:= x"4e1";
889--constant	botir7:						std_logic_vector(11 downto 0)	:= x"4e2";
890--constant	botir8:						std_logic_vector(11 downto 0)	:= x"4e3";
891--constant	botir9:						std_logic_vector(11 downto 0)	:= x"4e4";
892--constant	botir10:					std_logic_vector(11 downto 0)	:= x"4e5";
893--constant	botir11:					std_logic_vector(11 downto 0)	:= x"4e6";
894--constant	botir12:					std_logic_vector(11 downto 0)	:= x"4e7";
895--constant	botir13:					std_logic_vector(11 downto 0)	:= x"4e8";
896--constant	botir14:					std_logic_vector(11 downto 0)	:= x"4e9";
897--constant	botir15:					std_logic_vector(11 downto 0)	:= x"4ea";
898--constant	botir16:					std_logic_vector(11 downto 0)	:= x"4eb";
899--constant	botir17:					std_logic_vector(11 downto 0)	:= x"4ec";
900--constant	botir18:					std_logic_vector(11 downto 0)	:= x"4ed";
901--constant	botir19:					std_logic_vector(11 downto 0)	:= x"4ee";
902--constant	botir20:					std_logic_vector(11 downto 0)	:= x"4ef";
903--constant	botir21:					std_logic_vector(11 downto 0)	:= x"4f0";
904--constant	botir22:					std_logic_vector(11 downto 0)	:= x"4f1";
905--constant	botir23:					std_logic_vector(11 downto 0)	:= x"4f2";
906--constant	botir24:					std_logic_vector(11 downto 0)	:= x"4f3";
907--constant	botir25:					std_logic_vector(11 downto 0)	:= x"4f4";
908--constant	botir26:					std_logic_vector(11 downto 0)	:= x"4f5";
909--constant	botir27:					std_logic_vector(11 downto 0)	:= x"4f6";
910--constant	botir28:					std_logic_vector(11 downto 0)	:= x"4f7";
911--constant	botir29:					std_logic_vector(11 downto 0)	:= x"4f8";
912--constant	botir30:					std_logic_vector(11 downto 0)	:= x"4f9";
913--constant	botir31:					std_logic_vector(11 downto 0)	:= x"4fa";
914--constant	botir32:					std_logic_vector(11 downto 0)	:= x"4fb";
915--constant	botir33:					std_logic_vector(11 downto 0)	:= x"4fc";
916--constant	botir34:					std_logic_vector(11 downto 0)	:= x"4fd";
917--constant	botir35:					std_logic_vector(11 downto 0)	:= x"4fe";
918--constant	botir36:					std_logic_vector(11 downto 0)	:= x"4ff";
919--constant	botir37:					std_logic_vector(11 downto 0)	:= x"500";
920--constant	botir38:					std_logic_vector(11 downto 0)	:= x"501";
921
922-- LDDR
923constant	blddr5:						std_logic_vector(11 downto 0)	:= x"510";
924constant	blddr6:						std_logic_vector(11 downto 0)	:= x"511";
925--constant	blddr7:						std_logic_vector(11 downto 0)	:= x"512";
926--constant	blddr8:						std_logic_vector(11 downto 0)	:= x"513";
927--constant	blddr9:						std_logic_vector(11 downto 0)	:= x"514";
928--constant	blddr10:					std_logic_vector(11 downto 0)	:= x"515";
929--constant	blddr11:					std_logic_vector(11 downto 0)	:= x"516";
930--constant	blddr12:					std_logic_vector(11 downto 0)	:= x"517";
931--constant	blddr13:					std_logic_vector(11 downto 0)	:= x"518";
932--constant	blddr14:					std_logic_vector(11 downto 0)	:= x"519";
933--constant	blddr15:					std_logic_vector(11 downto 0)	:= x"51a";
934--constant	blddr16:					std_logic_vector(11 downto 0)	:= x"51b";
935--constant	blddr17:					std_logic_vector(11 downto 0)	:= x"51c";
936--constant	blddr18:					std_logic_vector(11 downto 0)	:= x"51d";
937--constant	blddr19:					std_logic_vector(11 downto 0)	:= x"51e";
938--constant	blddr20:					std_logic_vector(11 downto 0)	:= x"51f";
939--constant	blddr21:					std_logic_vector(11 downto 0)	:= x"520";
940--constant	blddr22:					std_logic_vector(11 downto 0)	:= x"521";
941--constant	blddr23:					std_logic_vector(11 downto 0)	:= x"522";
942--constant	blddr24:					std_logic_vector(11 downto 0)	:= x"523";
943--constant	blddr25:					std_logic_vector(11 downto 0)	:= x"524";
944--constant	blddr26:					std_logic_vector(11 downto 0)	:= x"525";
945--constant	blddr27:					std_logic_vector(11 downto 0)	:= x"526";
946--constant	blddr28:					std_logic_vector(11 downto 0)	:= x"527";
947--constant	blddr29:					std_logic_vector(11 downto 0)	:= x"528";
948--constant	blddr30:					std_logic_vector(11 downto 0)	:= x"529";
949--constant	blddr31:					std_logic_vector(11 downto 0)	:= x"52a";
950--constant	blddr32:					std_logic_vector(11 downto 0)	:= x"52b";
951--constant	blddr33:					std_logic_vector(11 downto 0)	:= x"52c";
952--constant	blddr34:					std_logic_vector(11 downto 0)	:= x"52d";
953--constant	blddr35:					std_logic_vector(11 downto 0)	:= x"52e";
954--constant	blddr36:					std_logic_vector(11 downto 0)	:= x"52f";
955--constant	blddr37:					std_logic_vector(11 downto 0)	:= x"530";
956--constant	blddr38:					std_logic_vector(11 downto 0)	:= x"531";
957
958-- CPDR
959constant	bcpdr5:						std_logic_vector(11 downto 0)	:= x"540";
960constant	bcpdr6:						std_logic_vector(11 downto 0)	:= x"541";
961--constant	bcpdr7:						std_logic_vector(11 downto 0)	:= x"542";
962--constant	bcpdr8:						std_logic_vector(11 downto 0)	:= x"543";
963--constant	bcpdr9:						std_logic_vector(11 downto 0)	:= x"544";
964--constant	bcpdr10:					std_logic_vector(11 downto 0)	:= x"545";
965--constant	bcpdr11:					std_logic_vector(11 downto 0)	:= x"546";
966--constant	bcpdr12:					std_logic_vector(11 downto 0)	:= x"547";
967--constant	bcpdr13:					std_logic_vector(11 downto 0)	:= x"548";
968--constant	bcpdr14:					std_logic_vector(11 downto 0)	:= x"549";
969--constant	bcpdr15:					std_logic_vector(11 downto 0)	:= x"54a";
970--constant	bcpdr16:					std_logic_vector(11 downto 0)	:= x"54b";
971--constant	bcpdr17:					std_logic_vector(11 downto 0)	:= x"54c";
972--constant	bcpdr18:					std_logic_vector(11 downto 0)	:= x"54d";
973--constant	bcpdr19:					std_logic_vector(11 downto 0)	:= x"54e";
974--constant	bcpdr20:					std_logic_vector(11 downto 0)	:= x"54f";
975--constant	bcpdr21:					std_logic_vector(11 downto 0)	:= x"550";
976--constant	bcpdr22:					std_logic_vector(11 downto 0)	:= x"551";
977--constant	bcpdr23:					std_logic_vector(11 downto 0)	:= x"552";
978--constant	bcpdr24:					std_logic_vector(11 downto 0)	:= x"553";
979--constant	bcpdr25:					std_logic_vector(11 downto 0)	:= x"554";
980--constant	bcpdr26:					std_logic_vector(11 downto 0)	:= x"555";
981--constant	bcpdr27:					std_logic_vector(11 downto 0)	:= x"556";
982--constant	bcpdr28:					std_logic_vector(11 downto 0)	:= x"557";
983--constant	bcpdr29:					std_logic_vector(11 downto 0)	:= x"558";
984--constant	bcpdr30:					std_logic_vector(11 downto 0)	:= x"559";
985--constant	bcpdr32:					std_logic_vector(11 downto 0)	:= x"55a";
986--constant	bcpdr33:					std_logic_vector(11 downto 0)	:= x"55b";
987--constant	bcpdr34:					std_logic_vector(11 downto 0)	:= x"55c";
988--constant	bcpdr35:					std_logic_vector(11 downto 0)	:= x"55d";
989--constant	bcpdr36:					std_logic_vector(11 downto 0)	:= x"55e";
990--constant	bcpdr37:					std_logic_vector(11 downto 0)	:= x"55f";
991--constant	bcpdr38:					std_logic_vector(11 downto 0)	:= x"560";
992--constant	bcpdr39:					std_logic_vector(11 downto 0)	:= x"561";
993
994-- INDR
995constant	bindr5:						std_logic_vector(11 downto 0)	:= x"570";
996constant	bindr6:						std_logic_vector(11 downto 0)	:= x"571";
997--constant	bindr7:						std_logic_vector(11 downto 0)	:= x"572";
998--constant	bindr8:						std_logic_vector(11 downto 0)	:= x"573";
999--constant	bindr9:						std_logic_vector(11 downto 0)	:= x"574";
1000--constant	bindr13:					std_logic_vector(11 downto 0)	:= x"575";
1001--constant	bindr10:					std_logic_vector(11 downto 0)	:= x"576";
1002--constant	bindr18:					std_logic_vector(11 downto 0)	:= x"577";
1003--constant	bindr12:					std_logic_vector(11 downto 0)	:= x"578";
1004--constant	bindr13:					std_logic_vector(11 downto 0)	:= x"579";
1005--constant	bindr14:					std_logic_vector(11 downto 0)	:= x"57a";
1006--constant	bindr15:					std_logic_vector(11 downto 0)	:= x"57b";
1007--constant	bindr16:					std_logic_vector(11 downto 0)	:= x"57c";
1008--constant	bindr17:					std_logic_vector(11 downto 0)	:= x"57d";
1009--constant	bindr18:					std_logic_vector(11 downto 0)	:= x"57e";
1010--constant	bindr19:					std_logic_vector(11 downto 0)	:= x"57f";
1011--constant	bindr20:					std_logic_vector(11 downto 0)	:= x"580";
1012--constant	bindr21:					std_logic_vector(11 downto 0)	:= x"581";
1013--constant	bindr22:					std_logic_vector(11 downto 0)	:= x"582";
1014--constant	bindr23:					std_logic_vector(11 downto 0)	:= x"583";
1015--constant	bindr24:					std_logic_vector(11 downto 0)	:= x"584";
1016--constant	bindr25:					std_logic_vector(11 downto 0)	:= x"585";
1017--constant	bindr26:					std_logic_vector(11 downto 0)	:= x"586";
1018--constant	bindr27:					std_logic_vector(11 downto 0)	:= x"587";
1019--constant	bindr28:					std_logic_vector(11 downto 0)	:= x"588";
1020--constant	bindr29:					std_logic_vector(11 downto 0)	:= x"589";
1021--constant	bindr30:					std_logic_vector(11 downto 0)	:= x"58a";
1022--constant	bindr31:					std_logic_vector(11 downto 0)	:= x"58b";
1023--constant	bindr32:					std_logic_vector(11 downto 0)	:= x"58c";
1024--constant	bindr33:					std_logic_vector(11 downto 0)	:= x"58d";
1025--constant	bindr34:					std_logic_vector(11 downto 0)	:= x"58e";
1026--constant	bindr35:					std_logic_vector(11 downto 0)	:= x"58f";
1027--constant	bindr36:					std_logic_vector(11 downto 0)	:= x"590";
1028--constant	bindr37:					std_logic_vector(11 downto 0)	:= x"591";
1029
1030-- OTDR
1031constant	botdr5:						std_logic_vector(11 downto 0)	:= x"5a0";
1032constant	botdr6:						std_logic_vector(11 downto 0)	:= x"5a1";
1033--constant	botdr7:						std_logic_vector(11 downto 0)	:= x"5a2";
1034--constant	botdr8:						std_logic_vector(11 downto 0)	:= x"5a3";
1035--constant	botdr9:						std_logic_vector(11 downto 0)	:= x"5a4";
1036--constant	botdr10:					std_logic_vector(11 downto 0)	:= x"5a5";
1037--constant	botdr11:					std_logic_vector(11 downto 0)	:= x"5a6";
1038--constant	botdr12:					std_logic_vector(11 downto 0)	:= x"5a7";
1039--constant	botdr13:					std_logic_vector(11 downto 0)	:= x"5a8";
1040--constant	botdr14:					std_logic_vector(11 downto 0)	:= x"5a9";
1041--constant	botdr15:					std_logic_vector(11 downto 0)	:= x"5aa";
1042--constant	botdr16:					std_logic_vector(11 downto 0)	:= x"5ab";
1043--constant	botdr17:					std_logic_vector(11 downto 0)	:= x"5ac";
1044--constant	botdr18:					std_logic_vector(11 downto 0)	:= x"5ad";
1045--constant	botdr19:					std_logic_vector(11 downto 0)	:= x"5ae";
1046--constant	botdr20:					std_logic_vector(11 downto 0)	:= x"5af";
1047--constant	botdr21:					std_logic_vector(11 downto 0)	:= x"5b0";
1048--constant	botdr22:					std_logic_vector(11 downto 0)	:= x"5b1";
1049--constant	botdr23:					std_logic_vector(11 downto 0)	:= x"5b2";
1050--constant	botdr24:					std_logic_vector(11 downto 0)	:= x"5b3";
1051--constant	botdr25:					std_logic_vector(11 downto 0)	:= x"5b4";
1052--constant	botdr26:					std_logic_vector(11 downto 0)	:= x"5b5";
1053--constant	botdr27:					std_logic_vector(11 downto 0)	:= x"5b6";
1054--constant	botdr28:					std_logic_vector(11 downto 0)	:= x"5b7";
1055--constant	botdr29:					std_logic_vector(11 downto 0)	:= x"5b8";
1056--constant	botdr30:					std_logic_vector(11 downto 0)	:= x"5b9";
1057--constant	botdr31:					std_logic_vector(11 downto 0)	:= x"5ba";
1058--constant	botdr32:					std_logic_vector(11 downto 0)	:= x"5bb";
1059--constant	botdr33:					std_logic_vector(11 downto 0)	:= x"5bc";
1060--constant	botdr34:					std_logic_vector(11 downto 0)	:= x"5bd";
1061--constant	botdr35:					std_logic_vector(11 downto 0)	:= x"5be";
1062--constant	botdr36:					std_logic_vector(11 downto 0)	:= x"5bf";
1063--constant	botdr37:					std_logic_vector(11 downto 0)	:= x"5c0";
1064--constant	botdr38:					std_logic_vector(11 downto 0)	:= x"5c1";
1065
1066-- end of ED prefixed opcodes
1067
1068-- index register instructions
1069constant	index4:						std_logic_vector(11 downto 0)	:= x"5d0";
1070constant	index5:						std_logic_vector(11 downto 0)	:= x"5d1";
1071constant	index6:						std_logic_vector(11 downto 0)	:= x"5d2";
1072constant	index7:						std_logic_vector(11 downto 0)	:= x"5d3";
1073constant	index8:						std_logic_vector(11 downto 0)	:= x"5d4";
1074
1075-- alu ops on immediate operand, 7 cycles, 1 m1 cycle
1076constant	alui4:						std_logic_vector(11 downto 0)	:= x"5e0";
1077constant	alui5:						std_logic_vector(11 downto 0)	:= x"5e1";
1078
1079-- RST, 11 clock cycles, 1 m1 cycle
1080constant	rst4:						std_logic_vector(11 downto 0)	:= x"5f0";
1081constant	rst5:						std_logic_vector(11 downto 0)	:= x"5f1";
1082constant	rst6:						std_logic_vector(11 downto 0)	:= x"5f2";
1083constant	rst7:						std_logic_vector(11 downto 0)	:= x"5f3";
1084constant	rst8:						std_logic_vector(11 downto 0)	:= x"5f4";
1085
1086-- get next opcode byte
1087constant	nxtop1:						std_logic_vector(11 downto 0)	:= x"600";
1088constant	nxtop2:						std_logic_vector(11 downto 0)	:= x"601";
1089
1090-- get next operand byte
1091constant	nxtoprnd1:					std_logic_vector(11 downto 0)	:= x"610";
1092constant	nxtoprnd2:					std_logic_vector(11 downto 0)	:= x"611";
1093
1094-- general memory read
1095constant	genmemrd1:					std_logic_vector(11 downto 0)	:= x"620";
1096constant	genmemrd2:					std_logic_vector(11 downto 0)	:= x"621";
1097constant	genmemrd3:					std_logic_vector(11 downto 0)	:= x"622";
1098
1099-- general memory write
1100constant	genmemwrt1:					std_logic_vector(11 downto 0)	:= x"630";
1101constant	genmemwrt2:					std_logic_vector(11 downto 0)	:= x"631";
1102constant	genmemwrt3:					std_logic_vector(11 downto 0)	:= x"632";
1103constant	genmemwrt4:					std_logic_vector(11 downto 0)	:= x"633";
1104
1105-- for 2-byte operands
1106constant	obtain_2byte_operand1:		std_logic_vector(11 downto 0)	:= x"640";
1107constant	obtain_2byte_operand2:		std_logic_vector(11 downto 0)	:= x"641";
1108
1109-- for SP increment
1110constant	incSP1:						std_logic_vector(11 downto 0)	:= x"650";
1111
1112-- for SP decrement
1113constant	decSP1:						std_logic_vector(11 downto 0)	:= x"660";
1114
1115-- for handling non-maskable interrupts
1116constant	nmi1:						std_logic_vector(11 downto 0)	:= x"670";
1117
1118-- for handling maskable interrupts
1119constant	int1:						std_logic_vector(11 downto 0)	:= x"680";
1120
1121-- index register bit operations
1122constant	index_bit5:					std_logic_vector(11 downto 0)	:= x"690";
1123constant	index_bit6:					std_logic_vector(11 downto 0)	:= x"691";
1124constant	index_bit7:					std_logic_vector(11 downto 0)	:= x"692";
1125
1126-- BIT
1127constant	index_bit_bit8:				std_logic_vector(11 downto 0)	:= x"6a0";
1128
1129-- common state for saving index bit operation results other than BIT
1130constant	index_save8:				std_logic_vector(11 downto 0)	:= x"6b0";
1131
1132-- load index register with immediate operand
1133constant	ld_index_immediate5:		std_logic_vector(11 downto 0)	:= x"6c0";
1134constant	ld_index_immediate6:		std_logic_vector(11 downto 0)	:= x"6c1";
1135
1136-- add index register to register pair
1137constant	add_index_rp5:	   			std_logic_vector(11 downto 0)	:= x"6d0";
1138constant	add_index_rp6:  			std_logic_vector(11 downto 0)	:= x"6d1";
1139
1140-- store index register direct
1141constant	st_index_direct5:			std_logic_vector(11 downto 0)	:= x"6e0";
1142constant	st_index_direct6:			std_logic_vector(11 downto 0)	:= x"6e1";
1143
1144-- load index register direct
1145constant	ld_index_direct5:			std_logic_vector(11 downto 0)	:= x"6f0";
1146constant	ld_index_direct6:			std_logic_vector(11 downto 0)	:= x"6f1";
1147constant	ld_index_direct7:			std_logic_vector(11 downto 0)	:= x"6f2";
1148constant	ld_index_direct8:			std_logic_vector(11 downto 0)	:= x"6f3";
1149constant	ld_index_direct9:			std_logic_vector(11 downto 0)	:= x"6f4";
1150constant	ld_index_direct10:			std_logic_vector(11 downto 0)	:= x"6f5";
1151constant	ld_index_direct11:			std_logic_vector(11 downto 0)	:= x"6f6";
1152constant	ld_index_direct12:			std_logic_vector(11 downto 0)	:= x"6f7";
1153constant	ld_index_direct13:			std_logic_vector(11 downto 0)	:= x"6f8";
1154constant	ld_index_direct14:			std_logic_vector(11 downto 0)	:= x"6f9";
1155
1156-- increment or decrement index register
1157constant	incdec_index5: 				std_logic_vector(11 downto 0)	:= x"700";
1158constant	incdec_index6:				std_logic_vector(11 downto 0)	:= x"701";
1159
1160-- increment or decrement memory at index register + offset
1161constant	incdec_index_memory5: 		std_logic_vector(11 downto 0)	:= x"710";
1162constant	incdec_index_memory6:		std_logic_vector(11 downto 0)	:= x"711";
1163
1164-- load immediate to index register + offset
1165constant	ld_index_memory_immed5:		std_logic_vector(11 downto 0)	:= x"720";
1166constant	ld_index_memory_immed6:		std_logic_vector(11 downto 0)	:= x"721";
1167
1168-- store 8 bit register to index register + offset
1169constant	st_index_memory5:			std_logic_vector(11 downto 0)	:= x"730";
1170
1171-- load 8 bit register from index register + offset
1172constant	ld_index_memory5:			std_logic_vector(11 downto 0)	:= x"740";
1173constant	ld_index_memory6:			std_logic_vector(11 downto 0)	:= x"741";
1174constant	ld_index_memory7:			std_logic_vector(11 downto 0)	:= x"742";
1175constant	ld_index_memory8:			std_logic_vector(11 downto 0)	:= x"743";
1176constant	ld_index_memory9:			std_logic_vector(11 downto 0)	:= x"744";
1177constant	ld_index_memory10:			std_logic_vector(11 downto 0)	:= x"745";
1178constant	ld_index_memory11:			std_logic_vector(11 downto 0)	:= x"746";
1179constant	ld_index_memory12:			std_logic_vector(11 downto 0)	:= x"747";
1180constant	ld_index_memory13:			std_logic_vector(11 downto 0)	:= x"748";
1181constant	ld_index_memory14:			std_logic_vector(11 downto 0)	:= x"749";
1182
1183-- 8 bit ALU operations involving memory pointed to by index register	+ offset
1184constant	index_alu_ops5:				std_logic_vector(11 downto 0)	:= x"750";
1185constant	index_alu_ops6:	 			std_logic_vector(11 downto 0)	:= x"751";
1186constant	index_alu_ops7:	 			std_logic_vector(11 downto 0)	:= x"752";
1187constant	index_alu_ops8:				std_logic_vector(11 downto 0)	:= x"753";
1188constant	index_alu_ops9:				std_logic_vector(11 downto 0)	:= x"754";
1189constant	index_alu_ops10:			std_logic_vector(11 downto 0)	:= x"755";
1190constant	index_alu_ops11:			std_logic_vector(11 downto 0)	:= x"756";
1191constant	index_alu_ops12:			std_logic_vector(11 downto 0)	:= x"757";
1192constant	index_alu_ops13:			std_logic_vector(11 downto 0)	:= x"758";
1193constant	index_alu_ops14:			std_logic_vector(11 downto 0)	:= x"759";
1194
1195-- pop index register off stack
1196constant	pop_index5:	  				std_logic_vector(11 downto 0)	:= x"770";
1197constant	pop_index6:	 				std_logic_vector(11 downto 0)	:= x"771";
1198constant	pop_index7:	 				std_logic_vector(11 downto 0)	:= x"772";
1199
1200-- push index register on stack
1201constant	push_index5:	  			std_logic_vector(11 downto 0)	:= x"780";
1202constant	push_index6:	 			std_logic_vector(11 downto 0)	:= x"781";
1203constant	push_index7:	 			std_logic_vector(11 downto 0)	:= x"782";
1204constant	push_index8:				std_logic_vector(11 downto 0)	:= x"783";
1205constant	push_index9:				std_logic_vector(11 downto 0)	:= x"784";
1206constant	push_index10:				std_logic_vector(11 downto 0)	:= x"785";
1207constant	push_index11:				std_logic_vector(11 downto 0)	:= x"786";
1208constant	push_index12:				std_logic_vector(11 downto 0)	:= x"787";
1209constant	push_index13:				std_logic_vector(11 downto 0)	:= x"788";
1210constant	push_index14:				std_logic_vector(11 downto 0)	:= x"789";
1211
1212-- SPI?
1213constant	sp_index5:	  				std_logic_vector(11 downto 0)	:= x"790";
1214
1215-- XTI?
1216constant	xtindex5:	  				std_logic_vector(11 downto 0)	:= x"7a0";
1217constant	xtindex6:	 				std_logic_vector(11 downto 0)	:= x"7a1";
1218constant	xtindex7:	 				std_logic_vector(11 downto 0)	:= x"7a2";
1219constant	xtindex8:					std_logic_vector(11 downto 0)	:= x"7a3";
1220constant	xtindex9:					std_logic_vector(11 downto 0)	:= x"7a4";
1221constant	xtindex10:					std_logic_vector(11 downto 0)	:= x"7a5";
1222constant	xtindex11:					std_logic_vector(11 downto 0)	:= x"7a6";
1223constant	xtindex12:					std_logic_vector(11 downto 0)	:= x"7a7";
1224constant	xtindex13:					std_logic_vector(11 downto 0)	:= x"7a8";
1225constant	xtindex14:					std_logic_vector(11 downto 0)	:= x"7a9";
1226
1227constant	test:						std_logic_vector(11 downto 0)	:= x"fff";
1228constant	waitstate:					std_logic_vector(11 downto 0)	:= x"ffe";
1229
1230end;