1use WORK.ALL;
2
3library IEEE;
4use IEEE.STD_LOGIC_1164.ALL;
5use ieee.numeric_std.all;
6use work.debugtools.all;
7
8entity iomapper is
9  port (Clk : in std_logic;
10        cpuclock : in std_logic;
11        pixelclk : in std_logic;
12        uartclock : in std_logic;
13        clock50mhz : in std_logic;
14        phi0 : in std_logic;
15        reset : in std_logic;
16        reset_out : out std_logic;
17        irq : out std_logic;
18        nmi : out std_logic;
19        restore_nmi : out std_logic;
20        cpu_hypervisor_mode : in std_logic;
21        address : in std_logic_vector(19 downto 0);
22        r : in std_logic;
23        w : in std_logic;
24        data_i : in std_logic_vector(7 downto 0);
25        data_o : out std_logic_vector(7 downto 0);
26        sd_data_o : out std_logic_vector(7 downto 0);
27        sector_buffer_mapped : out std_logic;
28
29        key_scancode : in unsigned(15 downto 0);
30        key_scancode_toggle : in std_logic;
31
32        reg_isr_out : out unsigned(7 downto 0);
33        imask_ta_out : out std_logic;
34
35        led : out std_logic := '0';
36        motor : out std_logic := '0';
37
38        ps2data : in std_logic;
39        ps2clock : in std_logic;
40
41        pixel_stream_in : in unsigned (7 downto 0);
42        pixel_y : in unsigned (11 downto 0);
43        pixel_valid : in std_logic;
44        pixel_newframe : in std_logic;
45        pixel_newraster : in std_logic;
46
47    ---------------------------------------------------------------------------
48    -- IO lines to the ethernet controller
49    ---------------------------------------------------------------------------
50    eth_mdio : inout std_logic;
51    eth_mdc : out std_logic;
52    eth_reset : out std_logic;
53    eth_rxd : in unsigned(1 downto 0);
54    eth_txd : out unsigned(1 downto 0);
55    eth_txen : out std_logic;
56    eth_rxdv : in std_logic;
57    eth_rxer : in std_logic;
58    eth_interrupt : in std_logic;
59
60        ----------------------------------------------------------------------
61        -- Flash RAM for holding config
62        ----------------------------------------------------------------------
63        QspiSCK : out std_logic;
64        QspiDB : inout std_logic_vector(3 downto 0);
65        QspiCSn : out std_logic;
66
67        -------------------------------------------------------------------------
68        -- Lines for the SDcard interface itself
69        -------------------------------------------------------------------------
70        cs_bo : out std_logic;
71        sclk_o : out std_logic;
72        mosi_o : out std_logic;
73        miso_i : in  std_logic;
74
75        ---------------------------------------------------------------------------
76        -- Lines for other devices that we handle here
77        ---------------------------------------------------------------------------
78        aclMISO : in std_logic;
79        aclMOSI : out std_logic;
80        aclSS : out std_logic;
81        aclSCK : out std_logic;
82        aclInt1 : in std_logic;
83        aclInt2 : in std_logic;
84
85        micData : in std_logic;
86        micClk : out std_logic;
87        micLRSel : out std_logic;
88
89        ampPWM : out std_logic;
90        ampSD : out std_logic;
91
92        tmpSDA : out std_logic;
93        tmpSCL : out std_logic;
94        tmpInt : in std_logic;
95        tmpCT : in std_logic;
96
97        sw : in std_logic_vector(15 downto 0);
98        btn : in std_logic_vector(4 downto 0);
99        seg_led : out unsigned(31 downto 0);
100
101        viciii_iomode : in std_logic_vector(1 downto 0);
102
103        colourram_at_dc00 : in std_logic;
104
105        ---------------------------------------------------------------------------
106        -- IO port to far call stack
107        ---------------------------------------------------------------------------
108        farcallstack_we : in std_logic;
109        farcallstack_addr : in std_logic_vector(8 downto 0);
110        farcallstack_din : in std_logic_vector(63 downto 0);
111        farcallstack_dout : out std_logic_vector(63 downto 0)
112
113        );
114end iomapper;
115
116architecture behavioral of iomapper is
117  component kickstart is
118    port (
119      Clk : in std_logic;
120      address : in std_logic_vector(13 downto 0);
121      we : in std_logic;
122      cs : in std_logic;
123      data_i : in std_logic_vector(7 downto 0);
124      data_o : out std_logic_vector(7 downto 0));
125  end component;
126
127  component sid6581 is
128    port (
129      clk_1MHz			: in  std_logic;		-- main SID clock signal
130      clk32				: in  std_logic;		-- main clock signal
131      reset				: in  std_logic;		-- high active signal (reset when reset = '1')
132      cs					: in  std_logic;		-- "chip select", when this signal is '1' this model can be accessed
133      we					: in std_logic;		-- when '1' this model can be written to, otherwise access is considered as read
134
135      addr				: in  unsigned(4 downto 0);	-- address lines
136      di					: in  unsigned(7 downto 0);	-- data in (to chip)
137      do					: out unsigned(7 downto 0);	-- data out	(from chip)
138      pot_x				: in  unsigned(7 downto 0);	-- paddle input-X
139      pot_y				: in  unsigned(7 downto 0);	-- paddle input-Y
140      audio_data		: out unsigned(17 downto 0)
141      );
142  end component;
143
144  component ethernet is
145  port (
146    clock : in std_logic;
147    clock50mhz : in std_logic;
148    reset : in std_logic;
149    irq : out std_logic := 'Z';
150
151    ---------------------------------------------------------------------------
152    -- IO lines to the ethernet controller
153    ---------------------------------------------------------------------------
154    eth_mdio : inout std_logic;
155    eth_mdc : out std_logic;
156    eth_reset : out std_logic;
157    eth_rxd : in unsigned(1 downto 0);
158    eth_txd : out unsigned(1 downto 0);
159    eth_txen : out std_logic;
160    eth_rxdv : in std_logic;
161    eth_rxer : in std_logic;
162    eth_interrupt : in std_logic;
163
164    -- Signals from the VIC-IV frame packer to supply the compressed video feed
165    buffer_moby_toggle : in std_logic := '0';
166    buffer_address : out unsigned(11 downto 0);
167    buffer_rdata : in unsigned(7 downto 0);
168
169    ---------------------------------------------------------------------------
170    -- keyboard event capture via ethernet
171    ---------------------------------------------------------------------------
172    eth_keycode_toggle : out std_logic;
173    eth_keycode : out unsigned(15 downto 0);
174
175    fastio_addr : in unsigned(19 downto 0);
176    fastio_write : in std_logic;
177    fastio_read : in std_logic;
178    fastio_wdata : in unsigned(7 downto 0);
179    fastio_rdata : out unsigned(7 downto 0)
180    );
181  end component;
182
183  component sdcardio is
184    port (
185      clock : in std_logic;
186      pixelclk : in std_logic;
187      reset : in std_logic;
188
189      ---------------------------------------------------------------------------
190      -- fast IO port (clocked at core clock). 1MB address space
191      ---------------------------------------------------------------------------
192      fastio_addr : in unsigned(19 downto 0);
193      fastio_read : in std_logic;
194      fastio_write : in std_logic;
195      fastio_wdata : in unsigned(7 downto 0);
196      fastio_rdata : out unsigned(7 downto 0);
197
198      -- If colour RAM is mapped at $DC00-$DFFF, then don't map sector buffer
199      colourram_at_dc00 : in std_logic;
200      viciii_iomode : in std_logic_vector(1 downto 0);
201
202      sectorbuffermapped : out std_logic;
203      sectorbuffermapped2 : out std_logic;
204      sectorbuffercs : in std_logic;
205
206      led : out std_logic := '0';
207      motor : out std_logic := '0';
208
209      -------------------------------------------------------------------------
210      -- Lines for the SDcard interface itself
211      -------------------------------------------------------------------------
212      cs_bo : out std_logic;
213      sclk_o : out std_logic;
214      mosi_o : out std_logic;
215      miso_i : in  std_logic;
216
217      ---------------------------------------------------------------------------
218      -- Lines for other devices that we handle here
219      ---------------------------------------------------------------------------
220      -- Accelerometer
221      aclMISO : in std_logic;
222      aclMOSI : out std_logic;
223      aclSS : out std_logic;
224      aclSCK : out std_logic;
225      aclInt1 : in std_logic;
226      aclInt2 : in std_logic;
227
228      -- Microphone
229      micData : in std_logic;
230      micClk : out std_logic;
231      micLRSel : out std_logic;
232
233      -- Audio in from digital SIDs
234      leftsid_audio : in unsigned(17 downto 0);
235      rightsid_audio : in unsigned(17 downto 0);
236
237      -- Audio output
238      ampPWM : out std_logic;
239      ampSD : out std_logic;
240
241      -- Temperature sensor
242      tmpSDA : out std_logic;
243      tmpSCL : out std_logic;
244      tmpInt : in std_logic;
245      tmpCT : in std_logic;
246
247      ----------------------------------------------------------------------
248      -- Flash RAM for holding config
249      ----------------------------------------------------------------------
250      QspiSCK : out std_logic;
251      QspiDB : inout std_logic_vector(3 downto 0);
252      QspiCSn : out std_logic;
253
254      last_scan_code : in std_logic_vector(12 downto 0);
255
256      -------------------------------------------------------------------------
257      -- And general switch inputs on the FPGA board (good as place as any here)
258      -------------------------------------------------------------------------
259      sw : in std_logic_vector(15 downto 0);
260      btn : in std_logic_vector(4 downto 0)
261
262      );
263  end component;
264
265  component cia6526 is
266    port (
267      cpuclock : in std_logic;
268      phi0 : in std_logic;
269      todclock : in std_logic;
270      reset : in std_logic;
271      irq : out std_logic := '1';
272
273      reg_isr_out : out unsigned(7 downto 0);
274      imask_ta_out : out std_logic;
275
276      ---------------------------------------------------------------------------
277      -- fast IO port (clocked at core clock). 1MB address space
278      ---------------------------------------------------------------------------
279      cs : in std_logic;
280      fastio_address : in unsigned(7 downto 0);
281      fastio_write : in std_logic;
282      fastio_wdata : in unsigned(7 downto 0);
283      fastio_rdata : out unsigned(7 downto 0);
284
285      portaout : out std_logic_vector(7 downto 0);
286      portain : in std_logic_vector(7 downto 0);
287
288      portbout : out std_logic_vector(7 downto 0);
289      portbin : in std_logic_vector(7 downto 0);
290
291      flagin : in std_logic;
292
293      pcout : out std_logic;
294
295      spout : out std_logic;
296      spin : in std_logic;
297
298      countout : out std_logic;
299      countin : in std_logic);
300  end component;
301  component keymapper is
302  port (
303    pixelclk : in std_logic;
304
305    last_scan_code : out std_logic_vector(12 downto 0);
306
307    nmi : out std_logic := 'Z';
308    reset : out std_logic := 'Z';
309
310    -- PS2 keyboard interface
311    ps2clock  : in  std_logic;
312    ps2data   : in  std_logic;
313    -- CIA ports
314    porta_in  : in  std_logic_vector(7 downto 0);
315    portb_in  : in  std_logic_vector(7 downto 0);
316    porta_out : out std_logic_vector(7 downto 0);
317    portb_out : out std_logic_vector(7 downto 0);
318
319    ---------------------------------------------------------------------------
320    -- keyboard event capture via ethernet
321    ---------------------------------------------------------------------------
322    eth_keycode_toggle : in std_logic;
323    eth_keycode : in unsigned(15 downto 0)
324
325    );
326  end component;
327
328  component framepacker is
329    port (
330      pixelclock : in std_logic;
331      ioclock : in std_logic;
332      hypervisor_mode : in std_logic;
333
334      pixel_stream_in : in unsigned (7 downto 0);
335      pixel_y : in unsigned (11 downto 0);
336      pixel_valid : in std_logic;
337      pixel_newframe : in std_logic;
338      pixel_newraster : in std_logic;
339
340      -- Signals for ethernet controller
341      buffer_moby_toggle : out std_logic := '0';
342      buffer_address : in unsigned(11 downto 0);
343      buffer_rdata : out unsigned(7 downto 0);
344
345      ---------------------------------------------------------------------------
346      -- fast IO port (clocked at CPU clock).
347      ---------------------------------------------------------------------------
348      fastio_addr : in unsigned(19 downto 0);
349      fastio_write : in std_logic;
350      fastio_read : in std_logic;
351      fastio_wdata : in unsigned(7 downto 0);
352      fastio_rdata : out unsigned(7 downto 0)
353      );
354  end component;
355
356  component farcallstack IS
357  PORT (
358    -- CPU fastio port
359    clka : IN STD_LOGIC;
360    ena : IN STD_LOGIC;
361    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
362    addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
363    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
364    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
365    -- CPU parallel push/pop port
366    clkb : IN STD_LOGIC;
367    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
368    addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
369    dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
370    doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
371    );
372  end component;
373
374  signal kickstartcs : std_logic;
375
376  signal reset_high : std_logic;
377
378  signal clock50hz : std_logic := '1';
379  constant divisor50hz : integer := 640000; -- 64MHz/50Hz/2;
380  signal counter50hz : integer := 0;
381
382  signal cia1cs : std_logic;
383  signal cia2cs : std_logic;
384
385  signal sectorbuffercs : std_logic;
386  signal sector_buffer_mapped_read : std_logic;
387
388  signal farcallstackcs : std_logic;
389  signal farcallstack_w : std_logic;
390  signal farcallstack_wdata : std_logic_vector(63 downto 0);
391  signal farcallstack_rdata : std_logic_vector(63 downto 0);
392
393  signal last_scan_code : std_logic_vector(12 downto 0);
394
395  signal cia1porta_out : std_logic_vector(7 downto 0);
396  signal cia1porta_in : std_logic_vector(7 downto 0);
397  signal cia1portb_out : std_logic_vector(7 downto 0);
398  signal cia1portb_in : std_logic_vector(7 downto 0);
399
400  signal leftsid_cs : std_logic;
401  signal leftsid_audio : unsigned(17 downto 0);
402  signal rightsid_cs : std_logic;
403  signal rightsid_audio : unsigned(17 downto 0);
404
405  signal spare_bits : unsigned(4 downto 0);
406
407  signal buffer_moby_toggle : std_logic;
408  signal buffer_address : unsigned(11 downto 0);
409  signal buffer_rdata : unsigned(7 downto 0);
410
411  signal eth_keycode_toggle : std_logic;
412  signal eth_keycode : unsigned(15 downto 0);
413
414begin
415  kickstartrom : kickstart port map (
416    clk     => clk,
417    address => address(13 downto 0),
418    we      => w,
419    cs      => kickstartcs,
420    data_i  => data_i,
421    data_o  => data_o);
422
423  framepacker0: framepacker port map (
424    ioclock => clk,
425    pixelclock => pixelclk,
426    hypervisor_mode => cpu_hypervisor_mode,
427
428    pixel_stream_in => pixel_stream_in,
429    pixel_y => pixel_y,
430    pixel_valid => pixel_valid,
431    pixel_newframe => pixel_newframe,
432    pixel_newraster => pixel_newraster,
433
434    buffer_moby_toggle => buffer_moby_toggle,
435    buffer_address => buffer_address,
436    buffer_rdata => buffer_rdata,
437
438    fastio_addr => unsigned(address(19 downto 0)),
439    fastio_write => w,
440    std_logic_vector(fastio_rdata) => data_o,
441    fastio_read => r,
442    fastio_wdata => unsigned(data_i)
443    );
444
445  cia1: cia6526 port map (
446    cpuclock => clk,
447    phi0 => phi0,
448    todclock => clock50hz,
449    reset => reset,
450    irq => irq,
451    reg_isr_out => reg_isr_out,
452    imask_ta_out => imask_ta_out,
453    cs => cia1cs,
454    fastio_address => unsigned(address(7 downto 0)),
455    fastio_write => w,
456    std_logic_vector(fastio_rdata) => data_o,
457    fastio_wdata => unsigned(data_i),
458    portaout => cia1porta_out,
459    portbout => cia1portb_out,
460    portain => cia1porta_in,
461    portbin => cia1portb_in,
462    flagin => '1',
463    spin => '1',
464    countin => '1'
465    );
466
467  cia2two: cia6526 port map (
468    cpuclock => clk,
469    phi0 => phi0,
470    todclock => clock50hz,
471    reset => reset,
472    irq => nmi,
473    cs => cia2cs,
474    fastio_address => unsigned(address(7 downto 0)),
475    fastio_write => w,
476    std_logic_vector(fastio_rdata) => data_o,
477    fastio_wdata => unsigned(data_i),
478
479    -- CIA ports not connected by default
480    portbin => x"ff",
481    portain => x"ff",
482    flagin => '1',
483    spin => '1',
484    countin => '1'
485    );
486
487  keymapper0 : keymapper port map (
488    pixelclk       => clk,
489    nmi => restore_nmi,
490    reset => reset_out,
491    ps2clock       => ps2clock,
492    ps2data        => ps2data,
493    last_scan_code => last_scan_code,
494--    key_status     => seg_led(1 downto 0),
495    porta_in       => cia1porta_out,
496    portb_in       => cia1portb_out,
497    porta_out      => cia1porta_in,
498    portb_out      => cia1portb_in,
499
500    -- remote keyboard input via ethernet
501--    eth_keycode_toggle => eth_keycode_toggle,
502--    eth_keycode => eth_keycode
503
504    -- remote
505    eth_keycode_toggle => key_scancode_toggle,
506    eth_keycode => key_scancode
507);
508
509  leftsid: sid6581 port map (
510    clk_1MHz => phi0,
511    clk32 => clk,
512    reset => reset_high,
513    cs => leftsid_cs,
514    we => w,
515    addr => unsigned(address(4 downto 0)),
516    di => unsigned(data_i),
517    std_logic_vector(do) => data_o,
518    pot_x => x"01",
519    pot_y => x"02",
520    audio_data => leftsid_audio);
521
522  rightsid: sid6581 port map (
523    clk_1MHz => phi0,
524    clk32 => clk,
525    reset => reset_high,
526    cs => rightsid_cs,
527    we => w,
528    addr => unsigned(address(4 downto 0)),
529    di => unsigned(data_i),
530    std_logic_vector(do) => data_o,
531    pot_x => x"03",
532    pot_y => x"04",
533    audio_data => rightsid_audio);
534
535  ethernet0 : ethernet port map (
536    clock50mhz => clock50mhz,
537    clock => clk,
538    reset => reset,
539    irq => irq,
540
541    ---------------------------------------------------------------------------
542    -- IO lines to the ethernet controller
543    ---------------------------------------------------------------------------
544    eth_mdio => eth_mdio,
545    eth_mdc => eth_mdc,
546    eth_reset => eth_reset,
547    eth_rxd => eth_rxd,
548    eth_txd => eth_txd,
549    eth_txen => eth_txen,
550    eth_rxdv => eth_rxdv,
551    eth_rxer => eth_rxer,
552    eth_interrupt => eth_interrupt,
553
554    buffer_moby_toggle => buffer_moby_toggle,
555    buffer_address => buffer_address,
556    buffer_rdata => buffer_rdata,
557
558    eth_keycode_toggle => eth_keycode_toggle,
559    eth_keycode => eth_keycode,
560
561    fastio_addr => unsigned(address),
562    fastio_write => w,
563    fastio_read => r,
564    fastio_wdata => unsigned(data_i),
565    std_logic_vector(fastio_rdata) => data_o
566    );
567
568  sdcard0 : sdcardio port map (
569    pixelclk => pixelclk,
570    clock => clk,
571    reset => reset,
572
573    fastio_addr => unsigned(address),
574    fastio_write => w,
575    fastio_read => r,
576    fastio_wdata => unsigned(data_i),
577    std_logic_vector(fastio_rdata) => data_o,
578    colourram_at_dc00 => colourram_at_dc00,
579    viciii_iomode => viciii_iomode,
580    sectorbuffermapped => sector_buffer_mapped,
581    sectorbuffermapped2 => sector_buffer_mapped_read,
582    sectorbuffercs => sectorbuffercs,
583
584    led => led,
585    motor => motor,
586
587    sw => sw,
588    btn => btn,
589    cs_bo => cs_bo,
590    sclk_o => sclk_o,
591    mosi_o => mosi_o,
592    miso_i => miso_i,
593
594    aclMISO => aclMISO,
595    aclMOSI => aclMOSI,
596    aclSS => aclSS,
597    aclSCK => aclSCK,
598    aclInt1 => aclInt1,
599    aclInt2 => aclInt2,
600
601    micData => micData,
602    micClk => micClk,
603    micLRSel => micLRSel,
604
605    leftsid_audio => leftsid_audio,
606    rightsid_audio => rightsid_audio,
607
608    ampSD => ampSD,
609    ampPWM => ampPWM,
610
611    tmpSDA => tmpSDA,
612    tmpSCL => tmpSCL,
613    tmpInt => tmpInt,
614    tmpCT => tmpCT,
615
616    QspiSCK => QspiSCK,
617    QspiDB => QspiDB,
618    QspiCSn => QspiCSn,
619
620    last_scan_code => last_scan_code
621
622    );
623
624  farcallstack0: farcallstack port map (
625    clka => clk,
626    ena => farcallstackcs,
627    wea(0) => w,
628    addra => address(11 downto 0),
629    dina => data_i,
630    douta => data_o,
631    clkb => cpuclock,
632    web(0) => farcallstack_w,
633    addrb => farcallstack_addr,
634    dinb => farcallstack_wdata,
635    doutb => farcallstack_rdata
636    );
637
638  process(reset)
639  begin
640    reset_high <= not reset;
641  end process;
642
643  process(clk)
644  begin
645    if rising_edge(clk) then
646      -- Generate 50Hz signal for TOD clock
647      -- (Note that we are a bit conflicted here, as our video mode is PALx4,
648      --  but at 60Hz.  We will make our CIAs take 50Hz like in most PAL countries
649      -- so that we don't confuse things too much.  We will probably add a 50Hz
650      -- raster interrupt filter to help music and games play at the right rate.)
651      if counter50hz<divisor50hz then
652        counter50hz <= counter50hz + 1;
653      else
654        clock50hz <= not clock50hz;
655        counter50hz <= 0;
656      end if;
657
658      seg_led(12) <= eth_keycode_toggle;
659      seg_led(11) <= last_scan_code(12);
660      seg_led(10 downto 0) <= unsigned(last_scan_code(10 downto 0));
661
662    end if;
663  end process;
664
665  process (r,w,address,cia1portb_in,cia1porta_out,colourram_at_dc00,
666           sector_buffer_mapped_read)
667  begin  -- process
668
669    if (r or w) = '1' then
670      -- @IO:GS $FFF8000-$FFFBFFF 16KB Kickstart/hypervisor ROM
671      -- @IO:GS $FFF8000 Hypervisor entry point when $D67F is written
672      if address(19 downto 14)&"00" = x"F8" then
673        kickstartcs <= cpu_hypervisor_mode;
674      else
675        kickstartcs <='0';
676      end if;
677
678      -- @IO:GS $FFF0000-$FFF0FFF - CPU far call stack (512x8 byte entries)
679      if address(19 downto 12) = x"F0" then
680        farcallstackcs <= '1';
681      else
682        farcallstackcs <= '0';
683      end if;
684
685      -- sdcard sector buffer: only mapped if no colour ram @ $DC00, and if
686      -- the sectorbuffer mapping flag is set
687      sectorbuffercs <= '0';
688      report "fastio address = $" & to_hstring(address) severity note;
689
690      if address(19 downto 16) = x"D"
691        and address(15 downto 14) = "00"
692        and address(11 downto 9)&'0' = x"E"
693        and sector_buffer_mapped_read = '1' and colourram_at_dc00 = '0' then
694        sectorbuffercs <= '1';
695        report "selecting SD card sector buffer" severity note;
696      end if;
697      -- Also map SD card sector buffer at $FFD6000 - $FFD61FF regardless of
698      -- VIC-IV IO mode and mapping of colour RAM
699      if address(19 downto 8) = x"D60" or address(19 downto 8) = x"D61" then
700        sectorbuffercs <= '1';
701      end if;
702
703      -- Now map the SIDs
704      -- @IO:C64 $D440-$D47F = left SID
705      -- @IO:C64 $D400-$D43F = right SID
706      -- @IO:C64 $D480-$D4FF = repeated images of SIDs
707      -- Presumably repeated through to $D5FF.  But we will repeat to $D4FF only
708      -- so that we can use $D500-$D5FF for other stuff.
709      case address(19 downto 8) is
710        when x"D04" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
711        when x"D14" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
712        when x"D24" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
713        when x"D34" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
714        when others => leftsid_cs <= '0'; rightsid_cs <= '0';
715      end case;
716
717      -- $D500 - $D5FF is not currently used.  Probably use some for FPU.
718
719      -- $D600 - $D60F is reserved for 6551 serial UART emulation for C65
720      -- compatibility (6551 actually only has 4 registers).
721      -- 6551 is not currently implemented, so this is just unmapped for now,
722      -- except for any read values required to allow the C65 ROM to function.
723
724      -- Hypervisor control (only visible from hypervisor mode) $D640 - $D67F
725      -- The hypervisor is a CPU provided function.
726
727      -- SD controller and miscellaneous hardware (microphone, accelerometer etc)
728      -- uses $D680 - $D6FF
729
730      -- CPU uses $FFD{0,1,2,3}700 for DMAgic and other CPU-hosted IO registers.
731
732      -- Now map the CIAs.
733
734      -- These are a bit fun, because they only get mapped if colour RAM isn't
735      -- being mapped in $DC00-$DFFF using the C65 2K colour ram register
736      cia1cs <='0';
737      cia2cs <='0';
738      if colourram_at_dc00='0' and sector_buffer_mapped_read='0' then
739        case address(19 downto 8) is
740          when x"D0C" => cia1cs <='1';
741          when x"D1C" => cia1cs <='1';
742          when x"D2C" => cia1cs <='1';
743          when x"D3C" => cia1cs <='1';
744          when x"D0D" => cia2cs <='1';
745          when x"D1D" => cia2cs <='1';
746          when x"D2D" => cia2cs <='1';
747          when x"D3D" => cia2cs <='1';
748          when others => null;
749        end case;
750      end if;
751    else
752      cia1cs <= '0';
753      cia2cs <= '0';
754      kickstartcs <= '0';
755      sectorbuffercs <= '0';
756      leftsid_cs <= '0';
757      rightsid_cs <= '0';
758      farcallstackcs <= '0';
759    end if;
760  end process;
761
762end behavioral;
763