1entity tb_fsm_5s is
2end tb_fsm_5s;
3
4library ieee;
5use ieee.std_logic_1164.all;
6
7architecture behav of tb_fsm_5s is
8  signal clk : std_logic;
9  signal rst : std_logic;
10  signal din : std_logic;
11  signal done : std_logic;
12begin
13  dut: entity work.fsm_5s
14    port map (
15      done => done,
16      d => din,
17      clk => clk,
18      rst => rst);
19
20  process
21    constant dat : std_logic_vector := b"10010_10010_11000";
22    constant res : std_logic_vector := b"00001_00001_00000";
23    procedure pulse is
24    begin
25      clk <= '0';
26      wait for 1 ns;
27      clk <= '1';
28      wait for 1 ns;
29    end pulse;
30  begin
31    rst <= '1';
32    din <= '0';
33    pulse;
34    assert done = '0' severity failure;
35    --  Test the whole sequence.
36    rst <= '0';
37    for i in dat'range loop
38      din <= dat (i);
39      pulse;
40      assert done = res(i) severity failure;
41    end loop;
42    wait;
43  end process;
44end behav;
45