1library IEEE;
2use IEEE.std_logic_1164.all;
3use IEEE.numeric_std.all;
4
5entity bug2 is
6	generic(
7		W    : positive := 4;
8		N    : positive := 4
9	);
10	port(
11		clk     :  in std_ulogic;
12		reset_n :  in std_ulogic;
13                o : out std_ulogic
14	);
15end bug2;
16
17architecture behav of bug2 is
18	type queue_info_t is record
19		dummy : integer range 0 to W-1;
20		strb  : std_ulogic_vector(W-1 downto 0);
21	end record;
22
23	type queues_t is array (0 to N-1) of queue_info_t;
24	signal queues : queues_t;
25begin
26
27	process(clk, reset_n)
28		variable index : integer range 0 to N-1;
29	begin
30          if reset_n = '0' then
31            index := 0;
32          elsif rising_edge(clk) then
33            for i in 0 to W-1 loop
34              queues(index).strb(i) <= '0';
35            end loop;
36            index := (index + 1) mod N;
37          end if;
38	end process;
39
40        o <=  queues (0).strb (0);
41end architecture;
42