1entity tb_dpram1r is
2end tb_dpram1r;
3
4library ieee;
5use ieee.std_logic_1164.all;
6
7architecture behav of tb_dpram1r is
8  signal raddr : natural range 0 to 3;
9  signal rbit : natural range 0 to 7;
10  signal rdat : std_logic;
11  signal waddr : natural range 0 to 3;
12  signal wdat : std_logic_vector(7 downto 0);
13  signal clk : std_logic;
14begin
15  dut: entity work.dpram1r
16    port map (raddr => raddr, rbit => rbit, rdat => rdat,
17              waddr => waddr, wdat => wdat,
18              clk => clk);
19
20  process
21    procedure pulse is
22    begin
23      clk <= '0';
24      wait for 1 ns;
25      clk <= '1';
26      wait for 1 ns;
27    end pulse;
28  begin
29    raddr <= 0;
30    rbit <= 0;
31    waddr <= 1;
32    wdat <= x"e1";
33    pulse;
34
35    raddr <= 1;
36    rbit <= 0;
37    waddr <= 0;
38    wdat <= x"f0";
39    pulse;
40    assert rdat = '1' severity failure;
41
42    raddr <= 1;
43    rbit <= 1;
44    waddr <= 2;
45    wdat <= x"d2";
46    pulse;
47    assert rdat = '0' severity failure;
48
49    raddr <= 1;
50    rbit <= 7;
51    waddr <= 3;
52    wdat <= x"c3";
53    pulse;
54    assert rdat = '1' severity failure;
55
56    raddr <= 3;
57    rbit <= 7;
58    waddr <= 0;
59    wdat <= x"f0";
60    pulse;
61    assert rdat = '1' severity failure;
62
63    raddr <= 3;
64    rbit <= 5;
65    waddr <= 0;
66    wdat <= x"f0";
67    pulse;
68    assert rdat = '0' severity failure;
69
70    wait;
71  end process;
72end behav;
73