1entity tb_dpram2w is
2end tb_dpram2w;
3
4library ieee;
5use ieee.std_logic_1164.all;
6
7architecture behav of tb_dpram2w is
8  signal waddr : natural range 0 to 3;
9  signal wnib : natural range 0 to 1;
10  signal wdat : std_logic_vector (3 downto 0);
11  signal raddr : natural range 0 to 3;
12  signal rdat : std_logic_vector(7 downto 0);
13  signal clk : std_logic;
14begin
15  dut: entity work.dpram2w
16    port map (waddr => waddr, wnib => wnib, wdat => wdat,
17              raddr => raddr, rdat => rdat,
18              clk => clk);
19
20  process
21    procedure pulse is
22    begin
23      clk <= '0';
24      wait for 1 ns;
25      clk <= '1';
26      wait for 1 ns;
27    end pulse;
28  begin
29    waddr <= 0;
30    wnib <= 0;
31    wdat <= x"0";
32    raddr <= 1;
33    pulse;
34
35    waddr <= 0;
36    wnib <= 1;
37    wdat <= x"f";
38    raddr <= 1;
39    pulse;
40
41    waddr <= 1;
42    wnib <= 1;
43    wdat <= x"e";
44    raddr <= 0;
45    pulse;
46    assert rdat = x"f0" severity failure;
47
48    waddr <= 1;
49    wnib <= 0;
50    wdat <= x"1";
51    raddr <= 0;
52    pulse;
53    assert rdat = x"f0" severity failure;
54
55    waddr <= 3;
56    wnib <= 0;
57    wdat <= x"3";
58    raddr <= 1;
59    pulse;
60    assert rdat = x"e1" severity failure;
61
62    waddr <= 3;
63    wnib <= 1;
64    wdat <= x"c";
65    raddr <= 1;
66    pulse;
67    assert rdat = x"e1" severity failure;
68
69    waddr <= 2;
70    wnib <= 1;
71    wdat <= x"d";
72    raddr <= 3;
73    pulse;
74    assert rdat = x"c3" severity failure;
75
76    waddr <= 2;
77    wnib <= 0;
78    wdat <= x"2";
79    raddr <= 3;
80    pulse;
81    assert rdat = x"c3" severity failure;
82
83    waddr <= 1;
84    wnib <= 0;
85    wdat <= x"1";
86    raddr <= 2;
87    pulse;
88    assert rdat = x"d2" severity failure;
89
90    wait;
91  end process;
92end behav;
93