1entity tb_ram4 is 2end tb_ram4; 3 4library ieee; 5use ieee.std_logic_1164.all; 6 7architecture behav of tb_ram4 is 8 signal clk : std_logic; 9 signal en : std_logic; 10 signal we : std_logic; 11 signal addr : std_logic_vector(5 downto 0); 12 signal rdat : std_logic_vector(31 downto 0); 13 signal wdat : std_logic_vector(31 downto 0); 14begin 15 dut: entity work.ram4 16 port map (clkB => clk, enB => en, weB => we, addrB => addr, 17 diB => wdat, doB => rdat); 18 19 process 20 procedure pulse is 21 begin 22 clk <= '0'; 23 wait for 1 ns; 24 clk <= '1'; 25 wait for 1 ns; 26 end pulse; 27 begin 28 en <= '1'; 29 we <= '1'; 30 addr <= b"00_0000"; 31 wdat <= x"11_22_33_f0"; 32 pulse; 33 assert rdat = x"11_22_33_f0" severity failure; 34 35 addr <= b"00_0001"; 36 wdat <= x"11_22_33_f1"; 37 pulse; 38 assert rdat = x"11_22_33_f1" severity failure; 39 40 -- Read. 41 we <= '0'; 42 addr <= b"00_0000"; 43 wdat <= x"ff_22_33_f1"; 44 pulse; 45 assert rdat = x"11_22_33_f0" severity failure; 46 47 addr <= b"00_0001"; 48 wdat <= x"ff_22_33_f1"; 49 pulse; 50 assert rdat = x"11_22_33_f1" severity failure; 51 52 -- Disable. 53 en <= '0'; 54 we <= '1'; 55 addr <= b"00_0000"; 56 wdat <= x"11_22_33_f0"; 57 pulse; 58 assert rdat = x"11_22_33_f1" severity failure; 59 60 wait; 61 end process; 62end behav; 63