1architecture spin1 of leds is 2 signal nrst : std_logic := '0'; 3 signal clk_4hz: std_logic; 4 signal leds : std_ulogic_vector (1 to 5); 5begin 6 (led1, led2, led3, led4, led5) <= leds; 7 led6 <= '0'; 8 led7 <= '0'; 9 led8 <= '0'; 10 11 process (clk) 12 variable cnt : unsigned (1 downto 0) := "00"; 13 begin 14 if rising_edge (clk) then 15 if cnt = 3 then 16 nrst <= '1'; 17 else 18 cnt := cnt + 1; 19 end if; 20 end if; 21 end process; 22 23 process (clk) 24 -- 3_000_000 is 0x2dc6c0 25 variable counter : unsigned (23 downto 0); 26 begin 27 if rising_edge(clk) then 28 if nrst = '0' then 29 counter := x"000000"; 30 else 31 if counter = 2_999_999 then 32 counter := x"000000"; 33 clk_4hz <= '1'; 34 else 35 counter := counter + 1; 36 clk_4hz <= '0'; 37 end if; 38 end if; 39 end if; 40 end process; 41 42 process (clk) 43 begin 44 if rising_edge(clk) then 45 if nrst = '0' then 46 -- Initialize 47 leds <= "11000"; 48 elsif clk_4hz = '1' then 49 -- Rotate 50 leds <= (leds (4), leds (1), leds (2), leds (3), '0'); 51 end if; 52 end if; 53 end process; 54end spin1; 55