1 2-- Copyright (C) 2001-2002 The University of Cincinnati. 3-- All rights reserved. 4 5-- This file is part of VESTs (Vhdl tESTs). 6 7-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE 8-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE 9-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, 10-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY 11-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR 12-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. 13 14-- By using or copying this Software, Licensee agrees to abide by the 15-- intellectual property laws, and all other applicable laws of the U.S., 16-- and the terms of this license. 17 18-- You may modify, distribute, and use the software contained in this 19-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, 20-- June 1991. A copy of this license agreement can be found in the file 21-- "COPYING", distributed with this archive. 22 23-- You should have received a copy of the GNU General Public License 24-- along with VESTs; if not, write to the Free Software Foundation, 25-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 27-- --------------------------------------------------------------------- 28-- 29-- $Id: test141.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ 30-- $Revision: 1.1 $ 31-- 32-- --------------------------------------------------------------------- 33 34---------------------------------------------------------------------- 35-- SIERRA REGRESSION TESTING MODEL 36-- Develooped at: 37-- Distriburted Processing Laboratory 38-- University of cincinnati 39-- Cincinnati 40---------------------------------------------------------------------- 41-- File : test141.ams 42-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) 43-- Created : May 2001 44---------------------------------------------------------------------- 45-- Description : 46-- this is the behavioral model of a simple error amplifier. 47-- the entity consists of a quatity port and the architecture consists 48-- of a simple simultaneos statement 49---------------------------------------------------------------------- 50PACKAGE electricalSystem IS 51 NATURE electrical IS real ACROSS real THROUGH ground reference; 52 FUNCTION SIN(X : real) RETURN real; 53 FUNCTION EXP(X : real) RETURN real; 54 FUNCTION SQRT(X : real) RETURN real; 55 FUNCTION POW(X,Y : real) RETURN real; 56-- subtype voltage is real; 57END PACKAGE electricalSystem; 58use work.electricalSystem.all; 59 60entity ErrorAmplifier is 61 generic( Gain : REAL := 10.0 -- amplifier gain 62 ); 63 port( terminal P_T,N_T: electrical; -- analog input pins 64 quantity Vout : out real -- analog output 65 ); 66end entity ErrorAmplifier; 67 68architecture Behavior of ErrorAmplifier is 69 70quantity DeltaV across P_T through N_T; -- differential input voltage 71begin 72e1: DeltaV== 1.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); 73e2: Vout == Gain*DeltaV; 74 75end architecture Behavior; 76