1
2-- Copyright (C) 2001-2002 The University of Cincinnati.
3-- All rights reserved.
4
5-- This file is part of VESTs (Vhdl tESTs).
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20-- June 1991. A copy of this license agreement can be found in the file
21-- "COPYING", distributed with this archive.
22
23-- You should have received a copy of the GNU General Public License
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26
27-- ---------------------------------------------------------------------
28--
29-- $Id: test161.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
30-- $Revision: 1.1 $
31--
32-- ---------------------------------------------------------------------
33
34----------------------------------------------------------------------
35-- SIERRA REGRESSION TESTING MODEL
36-- Develooped at:
37-- Distriburted Processing Laboratory
38-- University of Cincinnati
39----------------------------------------------------------------------
40-- File          : test150.ams
41-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
42-- Created       : May 2001
43----------------------------------------------------------------------
44-- Description :
45----------------------------------------------------------------------
46-- A simple RC  model...
47-- the test is done for checking the correct implementation
48--of the simple simultaneous equation statement with 'dot expression on RHS.
49--it checks nature declaration, terminal and quantity declarations.
50
51PACKAGE electricalSystem IS
52    NATURE electrical IS real ACROSS real THROUGH;
53    FUNCTION SIN(X : real) RETURN real;
54    FUNCTION EXP(X : real) RETURN real;
55END PACKAGE electricalSystem;
56use work.electricalSystem.all;
57
58entity test is
59end entity;
60
61architecture atest of test is
62terminal T1,T2:electrical;
63quantity V1 across I1 through T1 to T2;
64quantity V2 across I2 through T2;
65quantity VS across T1;
66
67begin
68
69e1:     V1 == I1*10.0;
70e2:     V2 == I1'integ/1.0e-12;
71
72esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
73
74end architecture atest;
75