1
2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20package arithmetic_ops is
21
22  -- code from book
23
24  procedure increment ( bv : inout bit_vector;  by : in integer := 1 );
25
26  procedure increment ( int : inout integer;  by : in integer := 1 );
27
28  -- end code from book
29
30end package arithmetic_ops;
31
32
33
34package body arithmetic_ops is
35
36  procedure increment ( bv : inout bit_vector;  by : in integer := 1 ) is
37  begin
38  end procedure increment;
39
40  procedure increment ( int : inout integer;  by : in integer := 1 ) is
41  begin
42  end procedure increment;
43
44end package body arithmetic_ops;
45
46
47
48----------------------------------------------------------------
49
50
51entity inline_06 is
52
53end entity inline_06;
54
55
56----------------------------------------------------------------
57
58
59library util;  use util.stimulus_generators.all;
60
61architecture test of inline_06 is
62
63  -- code from book
64
65  alias bv_increment is work.arithmetic_ops.increment [ bit_vector, integer ];
66
67  alias int_increment is work.arithmetic_ops.increment [ integer, integer ];
68
69  alias "*" is "and" [ bit, bit return bit ];
70
71  alias "+" is "or" [ bit, bit return bit ];
72
73  alias "-" is "not" [ bit return bit ];
74
75  alias high is std.standard.'1' [ return bit ];
76
77  -- end code from book
78
79  signal a, b, c, s : bit := '0';
80  signal test_vector : bit_vector(1 to 3);
81  signal test_high : bit := high;
82
83begin
84
85  -- code from book
86
87  s <= a * b + (-a) * c;
88
89  -- end code from book
90
91  stimulus : all_possible_values ( bv => test_vector,
92				   delay_between_values => 10 ns );
93
94  (a, b, c) <= test_vector;
95
96end architecture test;
97