1
2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20package physical_attributes is
21
22  -- code from book (in text)
23
24  attribute layout_ignore : boolean;
25  attribute pin_number : positive;
26
27  -- end code from book
28
29end package physical_attributes;
30
31
32-- code from book
33
34library ieee;  use ieee.std_logic_1164.all;
35use work.physical_attributes.all;
36
37entity \74x138\ is
38  generic ( Tpd : time );
39  port ( en1, en2a_n, en2b_n : in std_logic;
40         s0, s1, s2 : in std_logic;
41         y0, y1, y2, y3, y4, y5, y6, y7 : out std_logic );
42
43  attribute layout_ignore of Tpd : constant is true;
44
45  attribute pin_number of s0 : signal is 1;
46  attribute pin_number of s1 : signal is 2;
47  attribute pin_number of s2 : signal is 3;
48  attribute pin_number of en2a_n : signal is 4;
49  -- . . .
50
51end entity \74x138\;
52
53-- code from book
54