1 2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20package cell_attributes is 21 22 type length is range 0 to integer'high 23 units nm; 24 um = 1000 nm; 25 mm = 1000 um; 26 mil = 25400 nm; 27 end units length; 28 29 type coordinate is record 30 x, y : length; 31 end record coordinate; 32 33 attribute cell_position : coordinate; 34 35end package cell_attributes; 36 37 38 39entity CPU is 40end entity CPU; 41 42 43-- code from book 44 45architecture cell_based of CPU is 46 47 component fpu is 48 port ( -- . . . ); 49 -- not in book 50 port_name : bit := '0' ); 51 -- end not in book 52 end component; 53 54 use work.cell_attributes.all; 55 56 attribute cell_position of the_fpu : label is ( 540 um, 1200 um ); 57 58 -- . . . 59 60begin 61 62 the_fpu : component fpu 63 port map ( -- . . . ); 64 -- not in book 65 port_name => open ); 66 -- end not in book 67 68 -- . . . 69 70end architecture cell_based; 71 72-- end code from book 73