1
2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20entity add_with_overflow is
21end entity add_with_overflow;
22
23
24architecture test of add_with_overflow is
25begin
26
27-- code from book
28
29process is
30
31  procedure add_with_overflow ( a, b : in integer;
32                                sum : out integer;
33                                overflow : out boolean ) is -- . . .
34
35    -- not in book
36    begin
37    end;
38    -- end not in book
39
40  procedure add_with_overflow ( a, b : in bit_vector;
41                                sum : out bit_vector;
42                                overflow : out boolean ) is -- . . .
43
44    -- not in book
45    begin
46    end;
47    -- end not in book
48
49  attribute built_in : string;
50
51  attribute built_in of
52    add_with_overflow [ integer, integer,
53                        integer, boolean ] : procedure is "int_add_overflow";
54
55  attribute built_in of
56    add_with_overflow [ bit_vector, bit_vector,
57                        bit_vector, boolean ] : procedure is "bit_vector_add_overflow";
58
59begin
60  -- . . .
61  -- not in book
62  wait;
63  -- end not in book
64end process;
65
66-- end code from book
67
68end architecture test;
69