1 2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20entity controller is 21end entity controller; 22 23 24architecture test of controller is 25 26 signal clk : bit; 27 28 attribute synthesis_hint : string; 29 30begin 31 32 -- code from book 33 34 controller : process is 35 36 attribute synthesis_hint of control_loop : label is 37 "implementation:FSM(clk)"; 38 -- . . . 39 40 begin 41 -- . . . -- initialization 42 control_loop : loop 43 wait until clk = '1'; 44 -- . . . 45 end loop; 46 end process controller; 47 48 -- end code fom book 49 50end architecture test; 51