1 2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20entity flipflop is 21 generic ( Tsetup : delay_length ); 22 port ( clk, d : in bit; q : out bit ); 23end entity flipflop; 24 25 26-- code from book 27 28architecture behavior of flipflop is 29begin 30 31 timing_check : process (clk) is 32 begin 33 if clk = '1' then 34 assert d'last_event >= Tsetup 35 report "set up violation detected in " & timing_check'path_name 36 severity error; 37 end if; 38 end process timing_check; 39 40 -- . . . -- functionality 41 42end architecture behavior; 43 44-- end code from book 45