1 2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- analyze into resource library graphics 21 22package graphics_pkg is 23 24 attribute graphic_symbol : string; 25 attribute graphic_style : string; 26 27end package graphics_pkg; 28 29 30 31-- code from book 32 33library ieee; use ieee.std_logic_1164.all; 34library graphics; 35 36package gate_components is 37 38 use graphics.graphics_pkg.graphic_symbol, 39 graphics.graphics_pkg.graphic_style; 40 41 component and2 is 42 generic ( prop_delay : delay_length ); 43 port ( a, b : in std_logic; y : out std_logic ); 44 end component and2; 45 46 attribute graphic_symbol of and2 : component is "and2"; 47 attribute graphic_style of and2 : component is "color:default, weight:bold"; 48 49 -- . . . 50 51end package gate_components; 52 53-- end code from book 54