1
2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20package inline_09_defs is
21
22  attribute attr : integer;
23
24end package inline_09_defs;
25
26
27
28use work.inline_09_defs.all;
29
30entity e is
31  port ( p : in bit );
32  attribute attr of p : signal is 1;
33end entity e;
34
35
36architecture arch of e is
37begin
38
39  assert false report integer'image(p'attr);
40
41end architecture arch;
42
43
44
45use work.inline_09_defs.all;
46
47entity inline_09 is
48end entity inline_09;
49
50
51
52architecture test of inline_09 is
53
54  signal s : bit;
55
56  attribute attr of s : signal is 2;
57
58begin
59
60  -- code from book
61
62  c1 : entity work.e(arch)
63    port map ( p => s );
64
65  -- end code from book
66
67end architecture test;
68