1 2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20package timing_attributes is 21 22 attribute max_wire_delay : delay_length; 23 24end package timing_attributes; 25 26 27entity sequencer is 28end entity sequencer; 29 30 31-- code from book 32 33library ieee; use ieee.std_logic_1164.all; 34use work.timing_attributes.all; 35 36architecture structural of sequencer is 37 38 signal recovered_clk1, recovered_clk2 : std_logic; 39 signal test_enable : std_logic; 40 signal test_data : std_logic_vector(0 to 15); 41 42 attribute max_wire_delay of 43 recovered_clk1, recovered_clk2 : signal is 100 ps; 44 45 attribute max_wire_delay of others : signal is 200 ps; 46 47 -- . . . 48 49begin 50 -- . . . 51 -- not in book 52 assert false report time'image(recovered_clk1'max_wire_delay) severity note; 53 assert false report time'image(recovered_clk2'max_wire_delay) severity note; 54 assert false report time'image(test_enable'max_wire_delay) severity note; 55 assert false report time'image(test_data'max_wire_delay) severity note; 56 -- end not in book 57end architecture structural; 58 59-- code from book 60