1 2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20 21entity tb_flipflop is 22end entity tb_flipflop; 23 24 25architecture test of tb_flipflop is 26 27 signal clk, d, q : bit; 28 29begin 30 31 dut : entity work.flipflop(behavior) 32 generic map ( Tsetup => 3 ns ) 33 port map ( clk => clk, d => d, q => q ); 34 35 clk <= '1' after 10 ns, '0' after 20 ns; 36 37 d <= '1' after 8 ns; 38 39end architecture test; 40