1
2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20-- not in book
21
22entity graphics_engine is
23end entity graphics_engine;
24
25-- end not in book
26
27
28architecture behavioral of graphics_engine is
29
30  type point is array (1 to 3) of real;
31  type transformation_matrix is array (1 to 3, 1 to 3) of real;
32
33  signal p, transformed_p : point;
34  signal a : transformation_matrix;
35  signal clock : bit;
36  -- . . .
37
38begin
39
40  transform_stage : for i in 1 to 3 generate
41  begin
42
43    cross_product_transform : process is
44      variable result1, result2, result3 : real := 0.0;
45    begin
46      wait until clock = '1';
47      transformed_p(i) <= result3;
48      result3 := result2;
49      result2 := result1;
50      result1 :=  a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
51    end process cross_product_transform;
52
53  end generate transform_stage;
54
55  -- . . .    -- other stages in the pipeline, etc
56
57  -- not in book
58
59  clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
60
61  stimulus : process is
62  begin
63    a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
64    p <= ( 10.0, 10.0, 10.0 );
65    wait until clock = '0';
66    p <= ( 20.0, 20.0, 20.0 );
67    wait until clock = '0';
68    p <= ( 30.0, 30.0, 30.0 );
69    wait until clock = '0';
70    p <= ( 40.0, 40.0, 40.0 );
71    wait until clock = '0';
72    p <= ( 50.0, 50.0, 50.0 );
73    wait until clock = '0';
74    p <= ( 60.0, 60.0, 60.0 );
75
76    wait;
77  end process stimulus;
78
79  -- end not in book
80
81end architecture behavioral;
82