1 2 RUNNING THE GPL CVER INSTALLATION TEST 3 4First run Cver without any arguments to make sure Cver binary is 5correctly installed. Type "../../bin/cver" or if you have installed cver 6somewhere on your shell PATH just type "cver". The first line output 7Cver version number must match the version of your release directory. If 8version number does not match, you probably have your shell PATH environment 9variable set to execute an old version. 10 11If you are running on Unix/Linux based platforms, run the shell command 12script by typing: 13 14inst_tst.sh 15 16Correct installation is indicated by the following message with no diff 17command output lines before the message: 18 19>>>> Install test completed (this should be only printed message). 20 21The inst_tst.sh test script must either be in a directory on your PATH or in 22your current working directory. The inst_tst.sh script assumes you are 23running this test from the original Cver distribution directory tree. 24If you have already installed cver somewhere accessible from your OS 25shell PATH, edit the inst_tst.sh script and change: 26 27CVER="../../bin/cver -q " 28 29to 30 31CVER="cver -q" 32 33By convention the expected output files end with .plg suffix. 34 35------------------------------------------------------------------------- 36 37The installation script contains the following Verilog designs: 38 39minisim.v - the minisim model from the Thomas Moorby book used with 40 permission. This is a rather complicated behavioral model with 41 expected output supplied by Thomas/Moorby. 42 43instid.v - a test of defparam module customization (copying because Cver 44 does not flatten but rather uses improved non flattened based 45 addressing algorithm). 46 47aspike1.v - a test circuit that has a possibly questionable pulse/glitch 48 because it involves stL and stX. Five versions are run: 1) default 49 case with no pulse/glitch warnings or showing of X, 2) case that uses 50 +warn_canceled_e to cause warning messages to be emitted for pulses 51 (transitions that occur more frequently that gate or path delay), 52 3) case that uses +show_canceled_e to cause transition to X (showing of X) 53 at default leading edge of pulse. Output stays at X until next gate 54 transition because for pulses, a gate (or path) may or may not switch. 55 4) case that uses +show_canceled_e and +pulse_e_style_on_detect to test 56 transition to X (showing of X) when a pulse is detected instead of the 57 default at leading edge of pulse/glitch. 5) case that turns on event 58 tracing but does not use pulse/glitch analysis. The trace output 59 messages can also be used to detect potential pulse problems. 60 61 This example illustrates use of the various P1364 pulse analysis 62 options. 63 64 Notice because Cver scheduler is based on the more accurate Tegas 65 scheduler (c.f. various old papers by Syzgenda et. al. 66 - papers on www.pragmatic-c.com web site contains references), 67 spike analysis works for both path delays and gate delays. 68 69 70updjkff.v - a test using 2, 6 state udps from the Vcmp Valid SIM library. 71 72xx2bdel.v,xx2bpth.v,xx2bpth2.v - three variations on a small hierarchical 73 circuit. xx2bdel.v illustrates the new $openscanf, $scanf, and 74 $isetdelay distributed primitive delay annotation method. Unfortunately, 75 these system tasks do not follow the new Verilog 2000 P1364 file I/O 76 standard - we are working on changing to P1364 standard. xx2bpth.v uses 77 path delays instead of gate delays and xx2bpth2.v is encoded in terms of 78 a module that implements a not gate with a path delay. 79 80c880.v - flattened 700 gate level circuit from ISCAS. 81 82force01.v - force/release example 11.2 from OVI LRM 2.0 (p. 11-4). This 83 also tests interactive mode. 84 85vermemfil.v - example of how to use $scanf added system function (again 86 not yet same as Verilog 2000 File I/O options) to fill a memory using 87 just Cver functions. See the plimemfil.v (and .c) files for an example 88 of how to use PLI tf_strdelputp to fill a memory and plimemfil2.v for an 89 example of how to use PLI tf_propagatep to fill a memory. 90 91gatenots.v - a 13.8k gate hierarchical circuit. Since all outputs are 92 monitored at some time, it tests unoptimizable circuit. This 93 type of inverter chain circuit is used to bring up new ASIC processes. 94 Only a few patterns are run. 95 96The +printstats and +verbose statistics for this circuit are: 97 98----------------------------------------------------------------------------- 99+++ Printing Design Statistics +++ 100 Verbose mode statistics: 101 Design contains 3 module types. 102 112 (2300 flattened) ports collapsed. 103 9 gates (5400 flat) and 0 assigns (0 flat) disconnected by gate eater. 104 109 nets (5500 flat) disconnected by gate eater. 105 106 Design Module Table: 3 modules (1 top level): 107Module Level Cells-in Insts-in Primitives Assigns Nets Insts-of 108example_2b 2 0 10 0 1 653 1 109mod1 1 0 60 0 0 110 10 110dmod 0 0 0 23 0 24 600 111 ------ ------ ------ ------ ------ ------ 112Static Total: 0 70 23 1 787 113Flat Total: 0 610 13800 1 16153 611 114 115 Per Module Wiring Table (Task Variables Excluded): 116Module Ports(Bits) Wires(Bits) Registers(Bits) Memory(Cells, Bits) 117example_2b 650(650) 2(82) 1(10, 500) 118mod1 110(110) 119dmod 2(2) 22(22) 120 ------------ ------------- --------------- ------------------- 121Flat total: 2300(2300) 13850(13850) 2(82) 1(10, 500) 122 123 Design Usage Table: 124Type Class Static Flat Location 125 Number Number 126example_2b top 0 0 gatenots.v:1 127mod1 module 10 10 gatenots.v:312 128dmod module 60 600 gatenots.v:357 129not gate 23 13800 130wide-assign assign 1 1 131 132 Flattened Design: 610 instances, 0 udps, 13800 gates and 1 assigns. 133+++ End of Design Statistics +++ 134 Verbose mode statistics: 135 Design contains 3 module types. 136 112 (2300 flattened) ports collapsed. 137 9 gates (5400 flat) and 0 assigns (0 flat) disconnected by gate eater. 138 109 nets (5500 flat) disconnected by gate eater. 139 140 Begin load/optimize: 141 Approximately 396636 bytes storage allocated (excluding udps). 142 Begin simulation: 143 Approximately 718978 bytes storage allocated (excluding udps). 144 Verilog memories require 160 bytes (0.02% of total). 145----------------------------------------------------------------------------- 146 147arms_sim.v and armscnt.v - behavioral arms counter with large time scale 148 to test time scales. The circuit was part of the bench marks presented 149 by S. Coumeri from CMU at the 1994 IVC conference. 150 151dfpsetd.v - simple flip flop test, but shows SDF delay annotation using both 152 top level (no +[context]) +sdfannotate option and another file with 153 context. The dfpsetv.c PLI 2.0 model in examples.vpi uses the same 154 circuit but sets same delays using PLI vpi_put_delays and vpi_put_value 155 calls. SDF annotation also illustrates how assignment to defparams and 156 specparams used in delay expressions works. This example shows the 157 command line method for specifying SDF file. See systasks man page 158 for documentation on how to use $sdf_annotate system task to specify 159 SDF files. 160 161mipdnot1.v - simple not gate circuit that show how SDF MIPD delays work. 162 163sdfia04.v - example of use of instance and gate arrays with SDF back 164 annotation. 165 166dffn.v - pipeline pound parameters example from 1995 P1364 LRM section 7.1.6 167 168xplipnd.v - version of instid.v (above) that is changed to illustrate 169 new Verilog 2001 named pound parameter feature. Feature allows 170 passing only pound parameters to instances that need to be overridden. 171 172defsplt1.v - small example to test new parameter setting algorithm. 173 Example if difficult and it requires splitting module types because 174 vectors widths different between instance and re-evaluating parameters 175 because right hand side parameter definition expressions are set by 176 defparams. This example will fail in older versions of GPL Cver. 177