1 /* 2 * ********************************************************************* 3 * * Copyright (C) 1988, 1990 Stanford University. * 4 * * Permission to use, copy, modify, and distribute this * 5 * * software and its documentation for any purpose and without * 6 * * fee is hereby granted, provided that the above copyright * 7 * * notice appear in all copies. Stanford University * 8 * * makes no representations about the suitability of this * 9 * * software for any purpose. It is provided "as is" without * 10 * * express or implied warranty. Export of this software outside * 11 * * of the United States of America may require an export license. * 12 * ********************************************************************* 13 */ 14 15 #ifndef _NET_H 16 #define _NET_H 17 18 19 /* header for event driven mosfet simulator. Chris Terman (6/84) */ 20 21 typedef struct Event *evptr; 22 typedef struct Node *nptr; 23 typedef struct Trans *tptr; 24 typedef struct Input *iptr; 25 typedef struct Tlist *lptr; 26 typedef struct HistEnt *hptr; 27 typedef struct Bits *bptr; 28 typedef struct thevenin *Thev; 29 30 #ifndef _LOCTYPES_H 31 #include "loctypes.h" 32 #endif 33 34 #ifdef USER_SUBCKT 35 #include "../usersubckt/subckt.h" 36 #endif 37 38 struct Tlist 39 { 40 lptr next; /* next list element */ 41 tptr xtor; /* txtor connected to this node */ 42 }; 43 44 45 struct Event 46 { 47 evptr flink, blink; /* doubly-linked event list */ 48 evptr nlink; /* link for list of events for this node */ 49 nptr enode; /* node this event is all about */ 50 union 51 { 52 nptr cause; /* node which caused this event to happen */ 53 hptr hist; /* ptr. to history entry that queued this */ 54 Ulong oldt; /* original time for delayed events */ 55 } p; 56 Ulong ntime; /* time, in DELTAs, of this event */ 57 long delay; /* delay associated with this event */ 58 short rtime; /* rise/fall time, in DELTAs */ 59 Uchar eval; /* new value */ 60 Uchar type; /* type of event (for incremental only) */ 61 }; 62 63 typedef struct 64 { 65 short delay; /* delay from input */ 66 short rtime; /* rise/fall time */ 67 } RegTimes; 68 69 typedef struct 70 { 71 Uint delay : 12; /* delay from input */ 72 Uint rtime : 10; /* rise/fall time */ 73 Uint ptime : 10; /* punt time */ 74 } PuntTimes; 75 76 typedef struct HistEnt 77 { 78 hptr next; /* next transition in history */ 79 Ulong time : sizeof(Ulong) * 8 - 4; /* time of transition */ 80 Uint inp : 1; /* 1 if node became an input */ 81 Uint punt : 1; /* 1 if this event was punted */ 82 Uint val : 2; /* value: HIGH, LOW, or X */ 83 union 84 { 85 RegTimes r; 86 PuntTimes p; 87 int xx; 88 } t; 89 } HistEnt; 90 91 92 #define MAX_TIME ( (~((Ulong) 0)) >> 4 ) /* a huge time */ 93 #define TIME_BOUND (MAX_TIME + 1) /* out-of-bounds time value */ 94 95 typedef struct _aw { 96 nptr node; /* (assertion) which node we will check */ 97 char val ; /* (assertion) does the node have this value? */ 98 char *proc ; /* (schedule) procedure to apply under this condition */ 99 int tag; /* (schedule) tag number */ 100 struct _aw *nxt ; 101 } assertWhen ; 102 103 typedef assertWhen *awptr; 104 105 struct Node 106 { 107 nptr nlink; /* sundries list */ 108 evptr events; /* charge sharing event */ 109 lptr ngate; /* list of xtors w/ gates connected to this node */ 110 lptr nterm; /* list of xtors w/ src/drn connected to this node */ 111 nptr hnext; /* link in hash bucket */ 112 float ncap; /* capacitance of node in pf */ 113 float vlow; /* low logic threshold for node, normalized units */ 114 float vhigh; /* high logic threshold for node, normalized units */ 115 short tplh; /* low to high transition time in DELTA's */ 116 short tphl; /* high to low transition time in DELTA's */ 117 union 118 { 119 Ulong time; /* time, in DELTAs, of last transistion */ 120 float cap; /* incremental capacitance during net-changes */ 121 evptr event; /* non threaded events in incremental simulation */ 122 } c; 123 union 124 { 125 nptr cause; /* node which caused last transition of this node */ 126 hptr punts; /* punted events during incremental simulation */ 127 tptr tran; /* transistor into which stacked xtors were merged */ 128 } t; 129 short npot; /* current potential */ 130 short oldpot; /* old potential (for incremental simulation). */ 131 long nflags; /* flag word (see defs below) */ 132 char *nname; /* ascii name of node */ 133 union 134 { 135 Thev thev; /* used to temporarily store the thevenin structure */ 136 nptr next; /* used to build node lists during net changes */ 137 tptr tran; /* used to mark parallel transistors */ 138 } n; 139 HistEnt head; /* first entry in transition history */ 140 hptr curr; /* ptr. to current history entry */ 141 #ifdef POWER_EST 142 int toggles; /* number of transitions */ 143 #endif /* POWER_EST */ 144 #ifdef FAULT_SIM 145 HistEnt hchange; /* special entry to avoid changing the history */ 146 #endif 147 char awmask ; /* mask of values to cause evaluation of awpending */ 148 awptr awpending ; /* pending asswertWhen list */ 149 }; 150 151 152 typedef struct /* same as Res_1 but indexed dynamic resists */ 153 { 154 float dynres[ 2 ]; /* dynamic resistances [R_LOW - R_MAX] */ 155 float rstatic; /* static resistance of transistor */ 156 Uint width, length; /* transistor size in centimicrons */ 157 } Resists; 158 159 #define R_LOW 0 /* dynamic low resistance index */ 160 #define R_HIGH 1 /* dynamic high resistance index */ 161 162 #define dynlow dynres[ R_LOW ] /* abbrevations for above */ 163 #define dynhigh dynres[ R_HIGH ] 164 165 166 typedef union 167 { 168 Thev r; 169 tptr t; 170 int i; 171 } TCache; 172 173 typedef union 174 { 175 long pos; 176 tptr ptr; 177 } TPos; 178 179 struct Trans 180 { 181 nptr gate, source, drain; /* nodes to which trans is connected */ 182 TCache scache, dcache; /* caches to remember src/drn values */ 183 Uchar ttype; /* type of transistor */ 184 Uchar state; /* cache to remember current state */ 185 Uchar tflags; /* transistor flags */ 186 Uchar n_par; /* index into parallel list */ 187 Resists *r; /* transistor resistances */ 188 tptr tlink; /* next txtor in position hash table */ 189 TPos x, y; /* position in the layout (optional) */ 190 #ifdef USER_SUBCKT 191 char *subptr; /* pointer to subcircuit structure */ 192 #endif 193 }; 194 195 196 typedef struct Bits 197 { 198 bptr next; /* next bit vector in chain */ 199 char *name; /* name of this vector of bits */ 200 int traced; /* <>0 if this vector is being traced */ 201 int nbits; /* number of bits in this vector */ 202 nptr nodes[1]; /* pointers to the bits (nodes) */ 203 } Bits; 204 205 206 /* linked list of inputs */ 207 struct Input 208 { 209 iptr next; /* next element of list */ 210 nptr inode; /* pointer to this input node */ 211 }; 212 213 214 /* transistor types (ttype) */ 215 #define NCHAN 0 /* n-channel enhancement */ 216 #define PCHAN 1 /* p-channel enhancement */ 217 #define DEP 2 /* depletion */ 218 #define RESIST 3 /* simple two-terminal resistor */ 219 #define TYPERESERVED 4 /* reserved for future transistor types */ 220 #define SUBCKT 5 /* black box user code */ 221 222 #define ALWAYSON 0x02 /* transistors not affected by gate logic */ 223 224 #define GATELIST 0x08 /* set if gate of xistor is a node list */ 225 #define STACKED 0x10 /* transistor was stacked into gate list */ 226 #define ORED 0x20 /* result of or'ing parallel transistors */ 227 #define ORLIST 0x40 /* part of an or'ed transistor */ 228 #define TCAP 0x80 /* transistor capacitor (source == drain) */ 229 230 #ifndef USER_SUBCKT 231 #define NTTYPES 4 /* number of transistor types defined */ 232 #else 233 #define NTTYPES 6 /* number of transistor types defined */ 234 #endif 235 236 #define BASETYPE( T ) ( (T) & 0x07 ) 237 238 /* transistor states (state)*/ 239 #define OFF 0 /* non-conducting */ 240 #define ON 1 /* conducting */ 241 #define UNKNOWN 2 /* unknown */ 242 #define WEAK 3 /* weak */ 243 244 /* transistor temporary flags (tflags) */ 245 #define CROSSED 0x01 /* Mark for crossing a transistor */ 246 #define BROKEN 0x02 /* Mark a broken transistor to avoid loop */ 247 #define PBROKEN 0x04 /* Mark as broken a parallel transistor */ 248 #define PARALLEL 0x08 /* Mark as being a parallel transistor */ 249 #define ACTIVE_T 0x10 /* incremental status of transistor */ 250 251 /* figure what's on the *other* terminal node of a transistor */ 252 #define other_node( T, N ) ((T)->drain == (N) ? (T)->source : (T)->drain) 253 254 /* node potentials */ 255 #define LOW 0 /* logic low */ 256 #define X 1 /* unknown, intermediate, ... value */ 257 #define HIGH_Z 2 /* high impedence (not driven) */ 258 #define HIGH 3 /* logic high */ 259 #define N_POTS 4 /* number of potentials [LOW-HIGH] */ 260 261 #define DECAY 4 /* waiting to decay to X (only in events) */ 262 263 /* mask of node potentials, used by awpending */ 264 #define POT2MASK( p ) ( 1 << (1 + p) ) 265 266 /* possible values for nflags */ 267 #define DEVIATED 0x000001 /* node's state differs from hist */ 268 #define POWER_RAIL 0x000002 269 #define ALIAS 0x000004 270 #define USERDELAY 0x000008 271 #define INPUT 0x000010 272 #define WATCHED 0x000020 273 #define WATCHVECTOR 0x000040 274 #define STOPONCHANGE 0x000080 275 #define STOPVECCHANGE 0x000100 276 #define VISITED 0x000200 277 278 #define MERGED 0x000400 /* node is whithin a txtor stack */ 279 #define DELETED 0x000800 /* node was deleted */ 280 281 #define H_INPUT 0x001000 /* node is in high input list */ 282 #define L_INPUT 0x002000 /* node is in low input list */ 283 #define U_INPUT 0x003000 /* node is in U input list */ 284 #define X_INPUT 0x004000 /* node is in X input list */ 285 286 #define INPUT_MASK ( H_INPUT | L_INPUT | X_INPUT | U_INPUT ) 287 #define IsInList( flg ) ( (flg) & INPUT_MASK ) 288 #define INPUT_NUM( flg ) ( ((flg) & INPUT_MASK) >> 12 ) 289 290 #define CHANGED 0x008000 /* node is affected by a net change */ 291 #define STIM 0x010000 /* node is used as stimuli */ 292 #define ACTIVE_CL 0x020000 /* node is in an active cluster */ 293 #define WAS_ACTIVE 0x040000 /* set if node was ever active */ 294 295 #ifdef POWER_EST 296 #define POWWATCHED 0x080000 /* node's capacitance is being logged*/ 297 #define POWWATCHVECTOR 0x100000 /* vector version */ 298 #endif /* POWER_EST */ 299 300 #define SIM_ABORT 0x200000 /* set if unrecoverable error occurred */ 301 302 /* resistance types */ 303 #define STATIC 0 /* static resistance */ 304 #define DYNHIGH 1 /* dynamic-high resistance */ 305 #define DYNLOW 2 /* dynamic-low resistance */ 306 #define POWER 3 /* resist. for power calculation (unused) */ 307 #define R_TYPES 3 /* number of resistance contexts */ 308 309 /* Define TRUE and FALSE values */ 310 #define TRUE 1 311 #define FALSE 0 312 313 /* Possible simulator status */ 314 #define NORM_SIM 0 /* normal mode */ 315 #define INCR_SIM 01 /* incremental mode */ 316 #define OUT_OF_MEM 02 /* out of memory flag */ 317 318 /* Event Types (for incremental simulation only) */ 319 320 #define IS_INPUT 0x1 /* event makes node input */ 321 #define IS_XINPUT 0x2 /* event terminates input */ 322 323 #define REVAL 0x0 /* result of re-evaluation */ 324 #define DECAY_EV 0x1 /* node is decaying to X */ 325 #define PUNTED 0x3 /* previously punted event */ 326 327 /* events > THREAD are NOT threaded into node structure */ 328 #define THREAD 0x3 329 330 #define PENDING 0x4 /* pending from last run */ 331 #define STIMULI 0x8 /* self-scheduled stimuli */ 332 #define STIM_INP ( STIMULI | IS_INPUT ) 333 #define STIM_XINP ( STIMULI | IS_XINPUT ) 334 335 #define CHECK_PNT 0x10 /* next change in history */ 336 #define INP_EV ( CHECK_PNT | IS_INPUT ) 337 #define XINP_EV ( CHECK_PNT | IS_XINPUT ) 338 #define DELAY_CHK 0x20 /* delayed CHECK_PNT */ 339 #define DELAY_EV 0x40 /* last REVAL was delayed */ 340 341 #define CHNG_MODEL 0x80 /* change evaluation model */ 342 #define TRIGGER_EV 0x90 /* faultsim trigger event */ 343 #define TIMED_EV 0xa0 /* timed trigger event */ 344 345 346 /* Conversion macros between various time units */ 347 348 #ifndef _UNITS_H 349 #include "units.h" 350 #endif 351 352 #endif /* _NET_H */ 353