1v 20040710 1
2L 300 200 300 800 3 0 0 0 -1 -1
3T 300 0 9 8 1 0 0 0 1
47400
5L 300 800 700 800 3 0 0 0 -1 -1
6T 500 900 5 10 0 0 0 0 1
7device=7400
8T 500 1100 5 10 0 0 0 0 1
9slot=1
10T 500 1300 5 10 0 0 0 0 1
11numslots=4
12T 500 1500 5 10 0 0 0 0 1
13slotdef=1:1,2,3
14T 500 1700 5 10 0 0 0 0 1
15slotdef=2:4,5,6
16T 500 1900 5 10 0 0 0 0 1
17slotdef=3:9,10,8
18T 500 2100 5 10 0 0 0 0 1
19slotdef=4:12,13,11
20L 300 200 700 200 3 0 0 0 -1 -1
21A 700 500 300 270 180 3 0 0 0 -1 -1
22T 1000 100 8 10 1 1 0 0 1
23blah=This needs to be outside!
24V 1050 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
25P 1100 500 1300 500 1 0 1
26{
27T 1100 550 5 8 1 1 0 0 1
28pinnumber=3
29T 1100 450 5 8 0 1 0 2 1
30pinseq=3
31T 950 500 9 8 0 1 0 6 1
32pinlabel=Y
33T 950 500 5 8 0 1 0 8 1
34pintype=out
35}
36P 300 300 0 300 1 0 1
37{
38T 200 350 5 8 1 1 0 6 1
39pinnumber=2
40T 200 250 5 8 0 1 0 8 1
41pinseq=2
42T 350 300 9 8 0 1 0 0 1
43pinlabel=B
44T 350 300 5 8 0 1 0 2 1
45pintype=in
46}
47P 300 700 0 700 1 0 1
48{
49T 200 750 5 8 1 1 0 6 1
50pinnumber=1
51T 200 650 5 8 0 1 0 8 1
52pinseq=1
53T 350 700 9 8 0 1 0 0 1
54pinlabel=A
55T 350 700 5 8 0 1 0 2 1
56pintype=in
57}
58T 300 900 8 10 1 1 0 0 1
59refdes=U?
60T 500 2250 5 10 0 0 0 0 1
61footprint=DIP14
62T 500 2450 5 10 0 0 0 0 1
63description=4 NAND gates with 2 inputs
64T 500 2850 5 10 0 0 0 0 1
65net=Vcc:14
66T 500 3050 5 10 0 0 0 0 1
67net=GND:7
68T 500 2650 5 10 0 0 0 0 1
69documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
70T 1300 700 5 10 0 0 0 0 1
71symversion=1.999
72T 400 300 9 10 1 0 0 0 1
73minor
74