1-- Structural VAMS generated by gnetlist 2-- Secondary unit 3ARCHITECTURE transistor_test OF top_entity IS 4 terminal unnamed_net5 : electrical; 5 terminal unnamed_net4 : electrical; 6 terminal unnamed_net3 : electrical; 7 terminal unnamed_net2 : electrical; 8 terminal unnamed_net1 : electrical; 9BEGIN 10-- Architecture statement part 11 BJT1 : ENTITY BJT_transistor_simple(simple_arc) 12 GENERIC MAP ( 13 NEL => 5.0) 14 PORT MAP ( Base => unnamed_net2, 15 Collector => unnamed_net5, 16 Emitter => unnamed_net1); 17 18 VS_base : ENTITY VOLTAGE_SOURCE(sinusodial) 19 GENERIC MAP ( 20 amplitude => 1.0, 21 k => 150.0) 22 PORT MAP ( LT => unnamed_net3, 23 RT => unnamed_net1); 24 25 VS_collector : ENTITY VOLTAGE_SOURCE(sinusodial) 26 GENERIC MAP ( 27 amplitude => 2.0, 28 offset => 10.2, 29 k => 100.0) 30 PORT MAP ( LT => unnamed_net4, 31 RT => unnamed_net1); 32 33 RES_collecter : ENTITY RESISTOR 34 GENERIC MAP ( 35 r => 60.0) 36 PORT MAP ( RT => unnamed_net4, 37 LT => unnamed_net5); 38 39 RES_base : ENTITY RESISTOR 40 GENERIC MAP ( 41 r => 10000.0) 42 PORT MAP ( RT => unnamed_net2, 43 LT => unnamed_net3); 44 45 GND : ENTITY GROUND_NODE 46 PORT MAP ( T1 => unnamed_net1); 47 48END ARCHITECTURE transistor_test; 49