1entity proc5 is
2end entity;
3
4library ieee;
5use ieee.std_logic_1164.all;
6
7architecture test of proc5 is
8
9    procedure next_cycle(signal clk : in std_logic; n : in integer := 1) is
10    begin
11        for i in 1 to n loop
12            wait until rising_edge(clk);
13            wait for 1 ns;
14        end loop;
15    end procedure;
16
17    procedure create_clock
18        ( signal clk     : inout std_logic;
19          period         : in delay_length;
20          signal running : in boolean ) is
21    begin
22        if running then
23            clk <= not clk after period / 2;
24        end if;
25    end procedure;
26
27    signal running : boolean := true;
28
29    signal clk : std_logic := '1';
30
31begin
32
33    process (clk, running) is
34    begin
35        create_clock(clk, 20 ns, running);
36    end process;
37
38    process is
39    begin
40        next_cycle(clk, 50);
41        assert now = 1001 ns;
42        running <= false;
43        wait;
44    end process;
45
46end architecture;
47