1 // SPDX-License-Identifier: Apache-2.0
2 /*
3 * Copyright (C) 2019 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
4 */
5
6 #include <unistd.h>
7
8 #include <cstring>
9 #include <iostream>
10 #include <stdexcept>
11 #include <string>
12 #include <vector>
13
14 #include "jtag.hpp"
15 #include "bitparser.hpp"
16 #include "configBitstreamParser.hpp"
17 #include "jedParser.hpp"
18 #include "mcsParser.hpp"
19 #include "spiFlash.hpp"
20 #include "rawParser.hpp"
21
22 #include "display.hpp"
23 #include "xilinx.hpp"
24 #include "xilinxMapParser.hpp"
25 #include "part.hpp"
26 #include "progressBar.hpp"
27
Xilinx(Jtag * jtag,const std::string & filename,const std::string & file_type,Device::prog_type_t prg_type,const std::string & device_package,bool verify,int8_t verbose)28 Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
29 const std::string &file_type,
30 Device::prog_type_t prg_type,
31 const std::string &device_package, bool verify, int8_t verbose):
32 Device(jtag, filename, file_type, verify, verbose),
33 _device_package(device_package)
34 {
35 if (prg_type == Device::RD_FLASH) {
36 _mode = Device::READ_MODE;
37 } else if (!_file_extension.empty()) {
38 if (_file_extension == "mcs") {
39 _mode = Device::SPI_MODE;
40 } else if (_file_extension == "bit" || _file_extension == "bin") {
41 if (prg_type == Device::WR_SRAM)
42 _mode = Device::MEM_MODE;
43 else
44 _mode = Device::SPI_MODE;
45 } else if (_file_extension == "jed") {
46 _mode = Device::FLASH_MODE;
47 } else {
48 _mode = Device::SPI_MODE;
49 }
50 }
51
52 uint32_t idcode = _jtag->get_target_device_id();
53 std::string family = fpga_list[idcode].family;
54 if (family.substr(0, 5) == "artix") {
55 _fpga_family = ARTIX_FAMILY;
56 } else if (family == "spartan7") {
57 _fpga_family = SPARTAN7_FAMILY;
58 } else if (family == "zynq") {
59 _fpga_family = ZYNQ_FAMILY;
60 } else if (family == "kintex7") {
61 _fpga_family = KINTEX_FAMILY;
62 } else if (family == "spartan3") {
63 _fpga_family = SPARTAN3_FAMILY;
64 if (_mode != Device::MEM_MODE) {
65 throw std::runtime_error("Error: Only load to mem is supported");
66 }
67 } else if (family == "xcf") {
68 _fpga_family = XCF_FAMILY;
69 if (_mode == Device::MEM_MODE) {
70 throw std::runtime_error("Error: Only write or read is supported");
71 }
72 } else if (family == "spartan6") {
73 _fpga_family = SPARTAN6_FAMILY;
74 } else if (family == "xc2c") {
75 xc2c_init(idcode);
76 } else if (family == "xc9500xl") {
77 _fpga_family = XC95_FAMILY;
78 switch (idcode) {
79 case 0x09602093:
80 _xc95_line_len = 2;
81 break;
82 case 0x09604093:
83 _xc95_line_len = 4;
84 break;
85 case 0x09608093:
86 _xc95_line_len = 8;
87 break;
88 case 0x09616093:
89 _xc95_line_len = 16;
90 break;
91 }
92 } else {
93 _fpga_family = UNKNOWN_FAMILY;
94 }
95 }
~Xilinx()96 Xilinx::~Xilinx() {}
97
98 #define USER1 0x02
99 #define CFG_IN 0x05
100 #define USERCODE 0x08
101 #define IDCODE 0x09
102 #define ISC_ENABLE 0x10
103 #define JPROGRAM 0x0B
104 #define JSTART 0x0C
105 #define JSHUTDOWN 0x0D
106 #define ISC_PROGRAM 0x11
107 #define ISC_DISABLE 0x16
108 #define BYPASS 0xff
109
110 /* xc95 instructions set */
111 #define XC95_IDCODE 0xfe
112 #define XC95_ISC_ERASE 0xed
113 #define XC95_ISC_ENABLE 0xe9
114 #define XC95_ISC_DISABLE 0xf0
115 #define XC95_XSC_BLANK_CHECK 0xe5
116 #define XC95_ISC_PROGRAM 0xea
117 #define XC95_ISC_READ 0xee
118
119 #ifndef ETIME
120 #define ETIME 9935
121 #endif
122
reset()123 void Xilinx::reset()
124 {
125 _jtag->shiftIR(JSHUTDOWN, 6);
126 _jtag->shiftIR(JPROGRAM, 6);
127 _jtag->set_state(Jtag::RUN_TEST_IDLE);
128 _jtag->toggleClk(10000*12);
129
130 _jtag->set_state(Jtag::RUN_TEST_IDLE);
131 _jtag->toggleClk(2000);
132
133 _jtag->shiftIR(BYPASS, 6);
134 _jtag->set_state(Jtag::RUN_TEST_IDLE);
135 _jtag->toggleClk(2000);
136 }
137
idCode()138 int Xilinx::idCode()
139 {
140 int id = 0;
141 unsigned char tx_data[4]= {0x00, 0x00, 0x00, 0x00};
142 unsigned char rx_data[4];
143 _jtag->go_test_logic_reset();
144 _jtag->shiftIR(IDCODE, 6);
145 _jtag->shiftDR(tx_data, rx_data, 32);
146 id = ((rx_data[0] & 0x000000ff) |
147 ((rx_data[1] << 8) & 0x0000ff00) |
148 ((rx_data[2] << 16) & 0x00ff0000) |
149 ((rx_data[3] << 24) & 0xff000000));
150
151 /* workaround for XC95 with different
152 * IR length and IDCODE value
153 */
154 if (id == 0) {
155 _jtag->go_test_logic_reset();
156 _jtag->shiftIR(XC95_IDCODE, 8);
157 _jtag->shiftDR(tx_data, rx_data, 32);
158 id = ((rx_data[0] & 0x000000ff) |
159 ((rx_data[1] << 8) & 0x0000ff00) |
160 ((rx_data[2] << 16) & 0x00ff0000) |
161 ((rx_data[3] << 24) & 0xff000000));
162 }
163
164 return id;
165 }
166
program(unsigned int offset)167 void Xilinx::program(unsigned int offset)
168 {
169 ConfigBitstreamParser *bit;
170 bool reverse = false;
171
172 /* nothing to do */
173 if (_mode == Device::NONE_MODE || _mode == Device::READ_MODE)
174 return;
175
176 if (_mode == Device::FLASH_MODE && _file_extension == "jed") {
177 JedParser *jed;
178 printInfo("Open file ", false);
179
180 jed = new JedParser(_filename, _verbose);
181 if (jed->parse() == EXIT_FAILURE) {
182 printError("FAIL");
183 return;
184 }
185 printSuccess("DONE");
186
187 if (_fpga_family == XC95_FAMILY)
188 flow_program(jed);
189 else if (_fpga_family == XC2C_FAMILY)
190 xc2c_flow_program(jed);
191 else
192 throw std::runtime_error("Error: jed only supported for xc95 and xc2c");
193 return;
194 }
195
196 if (_fpga_family == XC95_FAMILY) {
197 printError("Only jed file and flash mode supported for XC95 CPLD");
198 return;
199 }
200
201 if (_mode == Device::MEM_MODE || _fpga_family == XCF_FAMILY)
202 reverse = true;
203
204 printInfo("Open file ", false);
205 try {
206 if (_file_extension == "bit")
207 bit = new BitParser(_filename, reverse, _verbose);
208 else if (_file_extension == "mcs")
209 bit = new McsParser(_filename, reverse, _verbose);
210 else
211 bit = new RawParser(_filename, reverse);
212 } catch (std::exception &e) {
213 printError("FAIL");
214 return;
215 }
216
217 printSuccess("DONE");
218
219 printInfo("Parse file ", false);
220 if (bit->parse() == EXIT_FAILURE) {
221 printError("FAIL");
222 delete bit;
223 return;
224 } else {
225 printSuccess("DONE");
226 }
227
228 if (_verbose)
229 bit->displayHeader();
230
231 if (_fpga_family == XCF_FAMILY) {
232 xcf_program(bit);
233 return;
234 }
235
236 if (_mode == Device::SPI_MODE) {
237 program_spi(bit, offset);
238 reset();
239 } else {
240 program_mem(bit);
241 }
242
243 delete bit;
244 }
245
load_bridge()246 bool Xilinx::load_bridge()
247 {
248 if (_device_package.empty()) {
249 printError("Can't program SPI flash: missing device-package information");
250 return false;
251 }
252
253 // DATA_DIR is defined at compile time.
254 std::string bitname = DATA_DIR "/openFPGALoader/spiOverJtag_";
255 bitname += _device_package + ".bit";
256
257 std::cout << "use: " << bitname << std::endl;
258
259 /* first: load spi over jtag */
260 try {
261 BitParser bridge(bitname, true, _verbose);
262 bridge.parse();
263 program_mem(&bridge);
264 } catch (std::exception &e) {
265 printError(e.what());
266 throw std::runtime_error(e.what());
267 }
268 return true;
269 }
270
program_spi(ConfigBitstreamParser * bit,unsigned int offset)271 void Xilinx::program_spi(ConfigBitstreamParser * bit, unsigned int offset)
272 {
273 /* first need to have bridge in RAM */
274 if (load_bridge() == false)
275 return;
276
277 uint8_t *data = bit->getData();
278 int length = bit->getLength() / 8;
279
280 SPIFlash spiFlash(this, (_verbose ? 1 : (_quiet ? -1 : 0)));
281 spiFlash.reset();
282 spiFlash.read_id();
283 spiFlash.display_status_reg(spiFlash.read_status_reg());
284 spiFlash.erase_and_prog(offset, data, length);
285
286 /* verify write if required */
287 if (_verify)
288 spiFlash.verify(offset, data, length, 256);
289 }
290
program_mem(ConfigBitstreamParser * bitfile)291 void Xilinx::program_mem(ConfigBitstreamParser *bitfile)
292 {
293 if (_file_extension.empty()) return;
294 std::cout << "load program" << std::endl;
295 unsigned char tx_buf, rx_buf;
296 /* comment TDI TMS TCK
297 * 1: On power-up, place a logic 1 on the TMS,
298 * and clock the TCK five times. This ensures X 1 5
299 * starting in the TLR (Test-Logic-Reset) state.
300 */
301 _jtag->go_test_logic_reset();
302 /*
303 * 2: Move into the RTI state. X 0 1
304 * 3: Move into the SELECT-IR state. X 1 2
305 * 4: Enter the SHIFT-IR state. X 0 2
306 * 5: Start loading the JPROGRAM instruction, 01011(4) 0 5
307 * LSB first:
308 * 6: Load the MSB of the JPROGRAM instruction
309 * when exiting SHIFT-IR, as defined in the 0 1 1
310 * IEEE standard.
311 * 7: Place a logic 1 on the TMS and clock the
312 * TCK five times. This ensures starting in X 1 5
313 * the TLR (Test-Logic-Reset) state.
314 */
315 _jtag->shiftIR(JPROGRAM, 6);
316 /* test */
317 tx_buf = BYPASS;
318 do {
319 _jtag->shiftIR(&tx_buf, &rx_buf, 6);
320 } while (!(rx_buf &0x01));
321 /*
322 * 8: Move into the RTI state. X 0 10,000(1)
323 */
324 _jtag->set_state(Jtag::RUN_TEST_IDLE);
325 _jtag->toggleClk(10000*12);
326 /*
327 * 9: Start loading the CFG_IN instruction,
328 * LSB first: 00101 0 5
329 * 10: Load the MSB of CFG_IN instruction when
330 * exiting SHIFT-IR, as defined in the 0 1 1
331 * IEEE standard.
332 */
333 _jtag->shiftIR(CFG_IN, 6);
334 /*
335 * 11: Enter the SELECT-DR state. X 1 2
336 */
337 _jtag->set_state(Jtag::SELECT_DR_SCAN);
338 /*
339 * 13: Shift in the FPGA bitstream. Bitn (MSB)
340 * is the first bit in the bitstream(2). bit1...bitn 0 (bits in bitstream)-1
341 * 14: Shift in the last bit of the bitstream.
342 * Bit0 (LSB) shifts on the transition to bit0 1 1
343 * EXIT1-DR.
344 */
345 /* GGM: TODO */
346 int byte_length = bitfile->getLength() / 8;
347 uint8_t *data = bitfile->getData();
348 int tx_len, tx_end;
349 int burst_len = byte_length / 100;
350
351 ProgressBar progress("Flash SRAM", byte_length, 50, _quiet);
352
353 for (int i=0; i < byte_length; i+=burst_len) {
354 if (i + burst_len > byte_length) {
355 tx_len = (byte_length - i) * 8;
356 /*
357 * 15: Enter UPDATE-DR state. X 1 1
358 */
359 tx_end = Jtag::UPDATE_DR;
360 } else {
361 tx_len = burst_len * 8;
362 /*
363 * 12: Enter the SHIFT-DR state. X 0 2
364 */
365 tx_end = Jtag::SHIFT_DR;
366 }
367 _jtag->shiftDR(data+i, NULL, tx_len, tx_end);
368 _jtag->flush();
369 progress.display(i);
370 }
371 progress.done();
372 /*
373 * 16: Move into RTI state. X 0 1
374 */
375 _jtag->set_state(Jtag::RUN_TEST_IDLE);
376 /*
377 * 17: Enter the SELECT-IR state. X 1 2
378 * 18: Move to the SHIFT-IR state. X 0 2
379 * 19: Start loading the JSTART instruction
380 * (optional). The JSTART instruction 01100 0 5
381 * initializes the startup sequence.
382 * 20: Load the last bit of the JSTART instruction. 0 1 1
383 * 21: Move to the UPDATE-IR state. X 1 1
384 */
385 _jtag->shiftIR(JSTART, 6, Jtag::UPDATE_IR);
386 /*
387 * 22: Move to the RTI state and clock the
388 * startup sequence by applying a minimum X 0 2000
389 * of 2000 clock cycles to the TCK.
390 */
391 _jtag->set_state(Jtag::RUN_TEST_IDLE);
392 _jtag->toggleClk(2000);
393 /*
394 * 23: Move to the TLR state. The device is
395 * now functional. X 1 3
396 */
397 _jtag->go_test_logic_reset();
398 }
399
dumpFlash(const std::string & filename,uint32_t base_addr,uint32_t len)400 bool Xilinx::dumpFlash(const std::string &filename,
401 uint32_t base_addr, uint32_t len)
402 {
403 if (_fpga_family == XC95_FAMILY || _fpga_family == XCF_FAMILY) {
404 std::string buffer;
405 if (_fpga_family == XC95_FAMILY) {
406 /* enable ISC */
407 flow_enable();
408 buffer = flow_read();
409 /* disable ISC */
410 flow_disable();
411 } else {
412 /* enable ISC */
413 xcf_flow_enable(0x34);
414 buffer = xcf_read();
415 /* disable ISC */
416 xcf_flow_disable();
417 }
418 printInfo("Open dump file ", false);
419 FILE *fd = fopen(filename.c_str(), "wb");
420 if (!fd) {
421 printError("FAIL");
422 return false;
423 }
424 printSuccess("DONE");
425
426 printInfo("Read flash ", false);
427 fwrite(buffer.c_str(), sizeof(uint8_t), buffer.size(), fd);
428
429 printSuccess("DONE");
430
431 fclose(fd);
432
433 return true;
434 }
435
436 int ret = true;
437 /* first need to have bridge in RAM */
438 if (load_bridge() == false)
439 return false;
440
441 /* prepare SPI access */
442 SPIFlash flash(this, _verbose);
443
444 try {
445 flash.reset();
446 ret = flash.dump(filename, base_addr, len, 256);
447 } catch (std::exception &e) {
448 printError(e.what());
449 ret = false;
450 }
451
452 /* reset device */
453 reset();
454
455 return ret;
456 }
457
458 /* */
459 /* internal flash (xc95) */
460 /* based on ISE xx_1532.bsd files */
461 /* */
462
flow_enable()463 void Xilinx::flow_enable()
464 {
465 uint8_t xfer_buf = 0x15;
466 _jtag->shiftIR(XC95_ISC_ENABLE, 8);
467 _jtag->shiftDR(&xfer_buf, NULL, 6);
468 _jtag->toggleClk(1);
469 }
470
flow_disable()471 void Xilinx::flow_disable()
472 {
473 _jtag->shiftIR(XC95_ISC_DISABLE, 8);
474 _jtag->toggleClk((_jtag->getClkFreq() * 100) / 1000000);
475 _jtag->shiftIR(BYPASS, 8);
476 _jtag->toggleClk(1);
477 }
478
flow_erase()479 bool Xilinx::flow_erase()
480 {
481 uint8_t xfer_buf[3] = {0x03, 0x00, 0x00};
482
483 printInfo("Erase flash ", false);
484
485 _jtag->shiftIR(XC95_ISC_ERASE, 8);
486 _jtag->shiftDR(xfer_buf, NULL, 18);
487 _jtag->toggleClk((_jtag->getClkFreq() * 400) / 1000);
488 _jtag->shiftDR(NULL, xfer_buf, 18);
489 if ((xfer_buf[0] & 0x03) != 0x01) {
490 printError("FAIL");
491 return false;
492 }
493
494 if (_verify) {
495 xfer_buf[0] = 0x03;
496 xfer_buf[1] = xfer_buf[2] = 0x00;
497
498 _jtag->shiftIR(XC95_XSC_BLANK_CHECK, 8);
499 _jtag->shiftDR(xfer_buf, NULL, 18);
500 _jtag->toggleClk(500);
501 _jtag->shiftDR(NULL, xfer_buf, 18);
502 if ((xfer_buf[0] & 0x03) != 0x01) {
503 printError("FAIL");
504 return false;
505 }
506 }
507 printSuccess("DONE");
508
509 return true;
510 }
511
flow_program(JedParser * jed)512 bool Xilinx::flow_program(JedParser *jed)
513 {
514 uint8_t wr_buf[16+2]; // largest section length
515 uint8_t rd_buf[16+3];
516
517 /* enable ISC */
518 flow_enable();
519
520 /* erase internal flash */
521 if (!flow_erase())
522 return false;
523
524 /* xc95 internal flash is written by sector
525 * for each one them 15 jed sections are used
526 */
527 size_t nb_section = jed->nb_section() / (15);
528
529 ProgressBar progress("Write Flash", nb_section, 50, _quiet);
530
531 for (size_t i = 0; i < nb_section; i++) {
532 uint16_t addr2 = i * 32;
533 for (int ii = 0; ii < 15; ii++) {
534 uint8_t mode = (ii == 14) ? 0x3 : 0x1;
535 int id = i * 15 + ii;
536
537 memcpy(wr_buf, jed->data_for_section(id)[0].c_str(),
538 _xc95_line_len);
539 wr_buf[_xc95_line_len] = (uint8_t) addr2&0xff;
540 wr_buf[_xc95_line_len+ 1 ] = (uint8_t)((addr2 >> 8) & 0xff);
541
542 _jtag->shiftIR(XC95_ISC_PROGRAM, 8);
543 _jtag->shiftDR(&mode, NULL, 2, Jtag::SHIFT_DR);
544 _jtag->shiftDR(wr_buf, NULL, 8 * (_xc95_line_len + 2));
545
546 if (ii == 14)
547 _jtag->toggleClk(20000);
548 else
549 _jtag->toggleClk(1);
550
551
552 if (ii == 14) {
553 mode = 0x00;
554 for (int loop_try = 0; loop_try < 32; loop_try++) {
555 _jtag->shiftIR(XC95_ISC_PROGRAM, 8);
556 _jtag->shiftDR(&mode, NULL, 2, Jtag::SHIFT_DR);
557 _jtag->shiftDR(wr_buf, NULL, 8 * (_xc95_line_len + 2));
558 _jtag->toggleClk((_jtag->getClkFreq() * 50) / 1000);
559 _jtag->shiftDR(NULL, rd_buf, 8 * (_xc95_line_len + 2) + 2);
560 if ((rd_buf[0] & 0x03) == 0x01)
561 break;
562 }
563
564 if ((rd_buf[0] & 0x03) != 0x01) {
565 progress.fail();
566 return false;
567 }
568 }
569 addr2 += ((ii+1) % 0x05) ? 1 : 4;
570 }
571 progress.display(i);
572 }
573 progress.done();
574
575 /* TODO: verify */
576 if (_verify) {
577 std::string flash = flow_read();
578 int flash_pos = 0;
579 ProgressBar progress2("Verify Flash", nb_section, 50, _quiet);
580 for (size_t section = 0; section < 108; section++) {
581 for (size_t subsection = 0; subsection < 15; subsection++) {
582 int id = section * 15 + subsection;
583 std::string content = jed->data_for_section(id)[0];
584 for (int col = 0; col < _xc95_line_len; col++, flash_pos++) {
585 if ((uint8_t)content[col] != (uint8_t)flash[flash_pos]) {
586 char error[256];
587 progress2.fail();
588 snprintf(error, sizeof(error),
589 "Error: wrong value: read %02x instead of %02x",
590 (uint8_t)flash[flash_pos], (uint8_t)content[col]);
591 printError(error);
592 flow_disable();
593 return false;
594 }
595 }
596 }
597 }
598 progress2.done();
599 }
600
601 /* disable ISC */
602 flow_disable();
603
604 return true;
605 }
606
flow_read()607 std::string Xilinx::flow_read()
608 {
609 uint8_t mode;
610 std::string buffer;
611 uint8_t wr_buf[16+2]; // largest section length
612 uint8_t rd_buf[16+2];
613 memset(wr_buf, 0xff, 16);
614
615 /* limit JTAG clock frequency to 1MHz */
616 if (_jtag->getClkFreq() > 1e6)
617 _jtag->setClkFreq(1e6);
618
619 ProgressBar progress("Read Flash", 108, 50, _quiet);
620
621 for (size_t section = 0; section < 108; section++) {
622 uint16_t addr2 = section * 32;
623 for (int subsection = 0; subsection < 15; subsection++) {
624 wr_buf[_xc95_line_len ] = (uint8_t)((addr2 ) & 0xff);
625 wr_buf[_xc95_line_len + 1] = (uint8_t)((addr2 >> 8) & 0xff);
626
627 mode = 3;
628 _jtag->shiftIR(XC95_ISC_READ, 8);
629 _jtag->shiftDR(&mode, NULL, 2, Jtag::SHIFT_DR);
630 _jtag->shiftDR(wr_buf, NULL, 8 * (_xc95_line_len + 2));
631
632 _jtag->toggleClk(1);
633
634 mode = 0;
635 _jtag->shiftDR(&mode, NULL, 2, Jtag::SHIFT_DR);
636 _jtag->shiftDR(NULL, rd_buf, 8 * (_xc95_line_len + 2));
637 for (int pos = 0; pos < _xc95_line_len; pos++)
638 buffer += rd_buf[pos];
639 addr2 += ((subsection+1) % 0x05) ? 1 : 4;
640 }
641 progress.display(section);
642 }
643 progress.done();
644
645 return buffer;
646 }
647
648 /* */
649 /* XCF Prom */
650 /* */
651
652 #define XCF_FVFY3 0xE2
653 #define XCF_ISCTESTSTATUS 0xE3
654 #define XCF_ISC_ENABLE 0xE8
655 #define XCF_ISC_PROGRAM 0xEA
656 #define XCF_ISC_ADDR_SHIFT 0xEB
657 #define XCF_ISC_ERASE 0xEC
658 #define XCF_ISC_DATA_SHIFT 0xED
659 #define XCF_CONFIG 0xEE
660 #define XCF_ISC_READ 0xeF
661 #define XCF_ISC_DISABLE 0xF0
662
xcf_flow_enable(uint8_t mode)663 void Xilinx::xcf_flow_enable(uint8_t mode)
664 {
665 _jtag->shiftIR(XCF_ISC_ENABLE, 8);
666 _jtag->shiftDR(&mode, NULL, 6);
667 _jtag->toggleClk(1);
668 }
669
xcf_flow_disable()670 void Xilinx::xcf_flow_disable()
671 {
672 _jtag->shiftIR(XCF_ISC_DISABLE, 8);
673 usleep(110000);
674 _jtag->shiftIR(BYPASS, 8);
675 _jtag->toggleClk(1);
676 }
677
xcf_flow_erase()678 bool Xilinx::xcf_flow_erase()
679 {
680 uint8_t xfer_buf[2] = {0x01, 0x00};
681
682 printInfo("Erase flash ", false);
683 xcf_flow_enable();
684
685 _jtag->shiftIR(XCF_ISC_ADDR_SHIFT, 8);
686 _jtag->shiftDR(xfer_buf, NULL, 16);
687 _jtag->toggleClk(1);
688
689 _jtag->shiftIR(XCF_ISC_ERASE, 8);
690 usleep(500000);
691
692 int i;
693 for (i = 0; i < 32; i++) {
694 _jtag->shiftIR(XCF_ISCTESTSTATUS, 8);
695 usleep(500000);
696 _jtag->shiftDR(NULL, xfer_buf, 8);
697 if ((xfer_buf[0] & 0x04))
698 break;
699 }
700
701 if (i == 32) {
702 printError("FAIL");
703 return false;
704 }
705
706 printSuccess("DONE");
707
708 xcf_flow_disable();
709
710 return true;
711 }
712
xcf_program(ConfigBitstreamParser * bitfile)713 bool Xilinx::xcf_program(ConfigBitstreamParser *bitfile)
714 {
715 uint8_t tx_buf[4096 / 8];
716 uint16_t pkt_len =
717 ((_jtag->get_target_device_id() == 0x05044093) ? 2048 : 4096) / 8;
718 uint8_t *data = bitfile->getData();
719 uint32_t data_len = bitfile->getLength() / 8;
720 uint32_t xfer_len, offset = 0;
721 uint32_t addr = 0;
722 int xfer_end;
723
724 /* limit JTAG clock frequency to 15MHz */
725 if (_jtag->getClkFreq() > 15e6)
726 _jtag->setClkFreq(15e6);
727
728 if (!xcf_flow_erase()) {
729 printError("flow erase failed");
730 return false;
731 }
732
733 xcf_flow_enable();
734
735 int blk_id = 0;
736
737 ProgressBar progress("Write PROM", (data_len / pkt_len), 50, _quiet);
738
739 while (data_len > 0) {
740 if (data_len < pkt_len) {
741 xfer_len = data_len;
742 xfer_end = Jtag::SHIFT_DR;
743 } else {
744 xfer_len = pkt_len;
745 xfer_end = Jtag::RUN_TEST_IDLE;
746 }
747
748 /* send data to PROM */
749 _jtag->shiftIR(XCF_ISC_DATA_SHIFT, 8);
750 _jtag->shiftDR(data+offset, NULL, xfer_len * 8, xfer_end);
751 if (xfer_len != pkt_len) {
752 uint32_t res = pkt_len - xfer_len;
753 memset(tx_buf, 0xff, res);
754 _jtag->shiftDR(tx_buf, NULL, res * 8);
755 }
756
757 _jtag->toggleClk(1);
758
759 /* send address */
760 tx_buf[0] = (addr >> 0) & 0x00ff;
761 tx_buf[1] = (addr >> 8) & 0x00ff;
762 _jtag->shiftIR(XCF_ISC_ADDR_SHIFT, 8);
763 _jtag->shiftDR(tx_buf, NULL, 16);
764 _jtag->toggleClk(1);
765
766 /* send program instruction */
767 _jtag->shiftIR(XCF_ISC_PROGRAM, 8);
768 usleep((addr == 0) ? 14000: 500);
769
770 /* wait until bit 3 != 1 */
771 int i;
772 for (i = 0; i < 29; i++) {
773 _jtag->shiftIR(XCF_ISCTESTSTATUS, 8);
774 usleep(500);
775 _jtag->shiftDR(NULL, tx_buf, 8);
776 if ((tx_buf[0] & 0x04))
777 break;
778 }
779
780 if (i == 29) {
781 progress.fail();
782 return false;
783 }
784
785 blk_id++;
786 offset += xfer_len;
787 addr += 32;
788 data_len -= xfer_len;
789 progress.display(blk_id);
790 }
791 progress.done();
792
793 /* program done */
794 _jtag->shiftIR(BYPASS, 8);
795 _jtag->toggleClk(1);
796
797 if (_verify) {
798 std::string flash = xcf_read();
799 uint32_t file_size = bitfile->getLength() / 8;
800 uint32_t prom_size = (uint32_t)flash.size();
801
802 uint32_t nb_bytes = (file_size > prom_size) ? prom_size : file_size;
803 ProgressBar progress2("Verify Flash", nb_bytes, 50, _quiet);
804
805 for (uint32_t pos = 0; pos < nb_bytes; pos++) {
806 if (data[pos] != (uint8_t)flash[pos]) {
807 progress2.fail();
808 char error[64];
809 snprintf(error, sizeof(error),
810 "Error: wrong value: read %02x instead of %02x",
811 (uint8_t)flash[pos], (uint8_t)data[pos]);
812 printError(error);
813 xcf_flow_disable();
814 return false;
815 }
816 progress.display(pos);
817 }
818 progress2.done();
819 }
820
821 _jtag->go_test_logic_reset();
822
823 xcf_flow_disable();
824
825 /* reconfigure FPGA */
826 _jtag->shiftIR(XCF_CONFIG, 8);
827 _jtag->toggleClk(1);
828 _jtag->shiftIR(BYPASS, 8);
829 _jtag->toggleClk(1);
830
831 return true;
832 }
833
xcf_read()834 std::string Xilinx::xcf_read()
835 {
836 uint32_t addr = 0;
837 uint8_t rx_buf[4096 / 8];
838 uint16_t pkt_len =
839 ((_jtag->get_target_device_id() == 0x05044093) ? 2048 : 4096) / 8;
840 uint16_t nb_section =
841 ((_jtag->get_target_device_id() == 0x05046093) ? 1024 : 512);
842
843 std::string buffer;
844
845 /* limit JTAG clock frequency to 15MHz */
846 if (_jtag->getClkFreq() > 15e6)
847 _jtag->setClkFreq(15e6);
848
849 ProgressBar progress("Read PROM", nb_section, 50, _quiet);
850
851 for (size_t section = 0; section < nb_section; section++) {
852 /* send address */
853 rx_buf[0] = (addr >> 0) & 0x00ff;
854 rx_buf[1] = (addr >> 8) & 0x00ff;
855 _jtag->shiftIR(XCF_ISC_ADDR_SHIFT, 8);
856 _jtag->shiftDR(rx_buf, NULL, 16);
857 _jtag->toggleClk(1);
858
859 /* send data to PROM */
860 _jtag->shiftIR(XCF_ISC_READ, 8);
861 usleep(50);
862 _jtag->shiftDR(NULL, rx_buf, pkt_len * 8);
863
864 for (int i = 0; i < pkt_len; i++)
865 buffer += rx_buf[i];
866
867 progress.display(section);
868 addr += 32;
869 }
870 progress.done();
871
872 return buffer;
873 }
874
875 /*--------------------------------------------------------*/
876 /* xc2c */
877 /*--------------------------------------------------------*/
878 #define XC2C_IDCODE 0x01
879 #define XC2C_ISC_DISABLE 0xc0
880 #define XC2C_VERIFY 0xd1
881 #define XC2C_ISC_ENABLE_OTF 0xe4
882 #define XC2C_ISC_WRITE 0xe6
883 #define XC2C_ISC_SRAM_READ 0xe7
884 #define XC2C_ISC_ENABLE 0xe8
885 #define XC2C_ISC_PROGRAM 0xea
886 #define XC2C_ISC_ERASE 0xed
887 #define XC2C_ISC_READ 0xee
888 #define XC2C_ISC_INIT 0xf0
889 #define XC2C_USERCODE 0xfd
890
891 /* xilinx programmer qualification specification 6.2
892 * directly reversed
893 */
894 static constexpr uint8_t _gray_code[256] = {
895 0x00, 0x80, 0xc0, 0x40, 0x60, 0xe0, 0xa0, 0x20,
896 0x30, 0xb0, 0xf0, 0x70, 0x50, 0xd0, 0x90, 0x10,
897 0x18, 0x98, 0xd8, 0x58, 0x78, 0xf8, 0xb8, 0x38,
898 0x28, 0xa8, 0xe8, 0x68, 0x48, 0xc8, 0x88, 0x08,
899 0x0c, 0x8c, 0xcc, 0x4c, 0x6c, 0xec, 0xac, 0x2c,
900 0x3c, 0xbc, 0xfc, 0x7c, 0x5c, 0xdc, 0x9c, 0x1c,
901 0x14, 0x94, 0xd4, 0x54, 0x74, 0xf4, 0xb4, 0x34,
902 0x24, 0xa4, 0xe4, 0x64, 0x44, 0xc4, 0x84, 0x04,
903 0x06, 0x86, 0xc6, 0x46, 0x66, 0xe6, 0xa6, 0x26,
904 0x36, 0xb6, 0xf6, 0x76, 0x56, 0xd6, 0x96, 0x16,
905 0x1e, 0x9e, 0xde, 0x5e, 0x7e, 0xfe, 0xbe, 0x3e,
906 0x2e, 0xae, 0xee, 0x6e, 0x4e, 0xce, 0x8e, 0x0e,
907 0x0a, 0x8a, 0xca, 0x4a, 0x6a, 0xea, 0xaa, 0x2a,
908 0x3a, 0xba, 0xfa, 0x7a, 0x5a, 0xda, 0x9a, 0x1a,
909 0x12, 0x92, 0xd2, 0x52, 0x72, 0xf2, 0xb2, 0x32,
910 0x22, 0xa2, 0xe2, 0x62, 0x42, 0xc2, 0x82, 0x02,
911 0x03, 0x83, 0xc3, 0x43, 0x63, 0xe3, 0xa3, 0x23,
912 0x33, 0xb3, 0xf3, 0x73, 0x53, 0xd3, 0x93, 0x13,
913 0x1b, 0x9b, 0xdb, 0x5b, 0x7b, 0xfb, 0xbb, 0x3b,
914 0x2b, 0xab, 0xeb, 0x6b, 0x4b, 0xcb, 0x8b, 0x0b,
915 0x0f, 0x8f, 0xcf, 0x4f, 0x6f, 0xef, 0xaf, 0x2f,
916 0x3f, 0xbf, 0xff, 0x7f, 0x5f, 0xdf, 0x9f, 0x1f,
917 0x17, 0x97, 0xd7, 0x57, 0x77, 0xf7, 0xb7, 0x37,
918 0x27, 0xa7, 0xe7, 0x67, 0x47, 0xc7, 0x87, 0x07,
919 0x05, 0x85, 0xc5, 0x45, 0x65, 0xe5, 0xa5, 0x25,
920 0x35, 0xb5, 0xf5, 0x75, 0x55, 0xd5, 0x95, 0x15,
921 0x1d, 0x9d, 0xdd, 0x5d, 0x7d, 0xfd, 0xbd, 0x3d,
922 0x2d, 0xad, 0xed, 0x6d, 0x4d, 0xcd, 0x8d, 0x0d,
923 0x09, 0x89, 0xc9, 0x49, 0x69, 0xe9, 0xa9, 0x29,
924 0x39, 0xb9, 0xf9, 0x79, 0x59, 0xd9, 0x99, 0x19,
925 0x11, 0x91, 0xd1, 0x51, 0x71, 0xf1, 0xb1, 0x31,
926 0x21, 0xa1, 0xe1, 0x61, 0x41, 0xc1, 0x81, 0x01,
927 };
928
xc2c_init(uint32_t idcode)929 void Xilinx::xc2c_init(uint32_t idcode)
930 {
931 _fpga_family = XC2C_FAMILY;
932 std::string model = fpga_list[idcode].model;
933 int underscore_pos = model.find_first_of('_', 0);
934 snprintf(_cpld_base_name, underscore_pos,
935 "%s", model.substr(0, underscore_pos).c_str());
936 switch ((idcode >> 16) & 0x3f) {
937 case 0x01: /* xc2c32 */
938 case 0x11: /* xc2c32a PC44 */
939 case 0x21: /* xc2c32a */
940 _cpld_nb_col = 260;
941 _cpld_nb_row = 48;
942 _cpld_addr_size = 6;
943 break;
944 case 0x05: /* xc2c64 */
945 case 0x25: /* xc2c64a */
946 _cpld_nb_col = 274;
947 _cpld_nb_row = 96;
948 _cpld_addr_size = 7;
949 break;
950 case 0x18: /* xc2c128 */
951 _cpld_nb_col = 752;
952 _cpld_nb_row = 80;
953 _cpld_addr_size = 7;
954 break;
955 case 0x14: /* xc2c256 */
956 _cpld_nb_col = 1364;
957 _cpld_nb_row = 96;
958 _cpld_addr_size = 7;
959 break;
960 case 0x15: /* xc2c384 */
961 _cpld_nb_col = 1868;
962 _cpld_nb_row = 120;
963 _cpld_addr_size = 7;
964 break;
965 case 0x17: /* xc2c512 */
966 _cpld_nb_col = 1980;
967 _cpld_nb_row = 160;
968 _cpld_addr_size = 8;
969 break;
970 default:
971 throw std::runtime_error("Error: unknown XC2C version");
972 }
973 _cpld_nb_row += 2; // 2 more row: done + sec and usercode
974 // datasheet table 2 p.15
975 }
976
977 /* reinit device
978 * datasheet table 47-48 p.61-62
979 */
xc2c_flow_reinit()980 void Xilinx::xc2c_flow_reinit()
981 {
982 uint8_t c = 0;
983 _jtag->shiftIR(XC2C_ISC_ENABLE_OTF, 8);
984 _jtag->shiftIR(XC2C_ISC_INIT, 8);
985 _jtag->toggleClk((_jtag->getClkFreq() * 20) / 1000);
986 _jtag->shiftIR(XC2C_ISC_INIT, 8);
987 _jtag->shiftDR(&c, NULL, 8);
988 _jtag->toggleClk((_jtag->getClkFreq() * 800) / 1000);
989 _jtag->shiftIR(XC2C_ISC_DISABLE, 8);
990 _jtag->shiftIR(BYPASS, 8);
991 }
992
993 /* full flash erase (with optional blank check)
994 * datasheet 12.1 (table41) p.56
995 */
xc2c_flow_erase()996 bool Xilinx::xc2c_flow_erase()
997 {
998 _jtag->shiftIR(XC2C_ISC_ENABLE_OTF, 8, Jtag::UPDATE_IR);
999 _jtag->shiftIR(XC2C_ISC_ERASE, 8);
1000 _jtag->toggleClk((_jtag->getClkFreq() * 100) / 1000);
1001 _jtag->shiftIR(XC2C_ISC_DISABLE, 8);
1002
1003 if (_verify) {
1004 std::string rx_buf = xc2c_flow_read();
1005 for (auto &val : rx_buf) {
1006 if ((uint8_t)val != 0xff) {
1007 printError("Erase: fails to verify blank check");
1008 return false;
1009 }
1010 }
1011 }
1012
1013 return true;
1014 }
1015
1016 /* read flash full content
1017 * return it has string buffer
1018 * table 45 - 46 p. 59-60
1019 */
xc2c_flow_read()1020 std::string Xilinx::xc2c_flow_read()
1021 {
1022 uint8_t rx_buf[249];
1023 uint32_t delay_loop = (_jtag->getClkFreq() * 20) / 1000000;
1024 uint16_t pos = 0;
1025 uint8_t addr_shift = 8 - _cpld_addr_size;
1026
1027 std::string buffer;
1028 buffer.resize(((_cpld_nb_col * _cpld_nb_row) + 7) / 8);
1029
1030 ProgressBar progress("Read Flash", _cpld_nb_row + 1, 50, _quiet);
1031
1032 _jtag->shiftIR(BYPASS, 8);
1033 _jtag->shiftIR(XC2C_ISC_ENABLE_OTF, 8);
1034 _jtag->shiftIR(XC2C_ISC_READ, 8);
1035
1036 /* send address
1037 * send addr 0 before loop because each row content
1038 * is followed by next addr (or dummy for the last row
1039 */
1040 /* send address */
1041 uint8_t addr = _gray_code[0] >> addr_shift;
1042 _jtag->shiftDR(&addr, NULL, _cpld_addr_size);
1043 /* wait 20us */
1044 _jtag->toggleClk(delay_loop);
1045
1046 for (size_t row = 1; row <= _cpld_nb_row; row++) {
1047 /* read nb_col bits, stay in shift_dr to send next addr */
1048 _jtag->shiftDR(NULL, rx_buf, _cpld_nb_col, Jtag::SHIFT_DR);
1049 /* send address */
1050 addr = _gray_code[row] >> addr_shift;
1051 _jtag->shiftDR(&addr, NULL, _cpld_addr_size);
1052 /* wait 20us */
1053 _jtag->toggleClk(delay_loop);
1054
1055 for (int i = 0; i < _cpld_nb_col; i++, pos++)
1056 if (rx_buf[i >> 3] & (1 << (i & 0x07)))
1057 buffer[pos >> 3] |= (1 << (pos & 0x07));
1058 else
1059 buffer[pos >> 3] &= ~(1 << (pos & 0x07));
1060
1061 progress.display(row);
1062 }
1063 progress.done();
1064
1065 _jtag->shiftIR(XC2C_ISC_DISABLE, Jtag::TEST_LOGIC_RESET);
1066
1067 return buffer;
1068 }
1069
xc2c_flow_program(JedParser * jed)1070 bool Xilinx::xc2c_flow_program(JedParser *jed)
1071 {
1072 uint8_t wr_buf[249]; // largest section length
1073 uint32_t delay_loop = (_jtag->getClkFreq() * 20) / 1000;
1074 uint8_t shift_addr = 8 - _cpld_addr_size;
1075
1076 /* map jed fuse using device map */
1077 printInfo("Map jed fuses: ", false);
1078 XilinxMapParser *map_parser;
1079 try {
1080 std::string mapname = ISE_DIR "/ISE_DS/ISE/xbr/data/" +
1081 std::string(_cpld_base_name) + ".map";
1082 map_parser = new XilinxMapParser(mapname, _cpld_nb_row, _cpld_nb_col,
1083 jed, 0xffffffff, _verbose);
1084 map_parser->parse();
1085 } catch(std::exception &e) {
1086 printError("FAIL");
1087 throw std::runtime_error(e.what());
1088 }
1089 printSuccess("DONE");
1090
1091 std::vector<std::string> listfuse = map_parser->cfg_data();
1092
1093 /* erase internal flash */
1094 printInfo("Erase Flash: ", false);
1095 if (!xc2c_flow_erase()) {
1096 printError("FAIL");
1097 throw std::runtime_error("Fail to erase interface flash");
1098 } else {
1099 printSuccess("DONE");
1100 }
1101
1102 ProgressBar progress("Write Flash", _cpld_nb_row, 50, _quiet);
1103
1104 _jtag->shiftIR(XC2C_ISC_ENABLE_OTF, 8);
1105 _jtag->shiftIR(XC2C_ISC_PROGRAM, 8);
1106
1107 uint16_t iter = 0;
1108 for (auto row : listfuse) {
1109 uint16_t pos = 0;
1110 uint8_t addr = _gray_code[iter] >> shift_addr;
1111 for (auto col : row) {
1112 if (col)
1113 wr_buf[pos >> 3] |= (1 << (pos & 0x07));
1114 else
1115 wr_buf[pos >> 3] &= ~(1 << (pos & 0x07));
1116 pos++;
1117 }
1118 _jtag->shiftDR(wr_buf, NULL, _cpld_nb_col, Jtag::SHIFT_DR);
1119 _jtag->shiftDR(&addr, NULL, _cpld_addr_size);
1120 _jtag->toggleClk(delay_loop);
1121
1122 iter++;
1123 }
1124
1125 /* done bit and usercode are shipped into listfuse
1126 * so only needs to send isc disable
1127 */
1128 _jtag->shiftIR(XC2C_ISC_DISABLE, 8);
1129
1130 if (_verify) {
1131 std::string rx_buffer = xc2c_flow_read();
1132 iter = 0;
1133 for (auto row : listfuse) {
1134 for (auto col : row) {
1135 if ((rx_buffer[iter >> 3] >> (iter & 0x07)) != col) {
1136 throw std::runtime_error("Program: verify failed");
1137 }
1138 iter++;
1139 }
1140 }
1141 }
1142
1143 /* reload */
1144 xc2c_flow_reinit();
1145
1146 return true;
1147 }
1148
1149 /* */
1150 /* SPI interface */
1151 /* */
1152
1153 /*
1154 * jtag : jtag interface
1155 * cmd : opcode for SPI flash
1156 * tx : buffer to send
1157 * rx : buffer to fill
1158 * len : number of byte to send/receive (cmd not comprise)
1159 * so to send only a cmd set len to 0 (or omit this param)
1160 */
spi_put(uint8_t cmd,uint8_t * tx,uint8_t * rx,uint32_t len)1161 int Xilinx::spi_put(uint8_t cmd,
1162 uint8_t *tx, uint8_t *rx, uint32_t len)
1163 {
1164 int xfer_len = len + 1 + ((rx == NULL) ? 0 : 1);
1165 uint8_t jtx[xfer_len];
1166 jtx[0] = McsParser::reverseByte(cmd);
1167 /* uint8_t jtx[xfer_len] = {McsParser::reverseByte(cmd)}; */
1168 uint8_t jrx[xfer_len];
1169 if (tx != NULL) {
1170 for (uint32_t i=0; i < len; i++)
1171 jtx[i+1] = McsParser::reverseByte(tx[i]);
1172 }
1173 /* addr BSCAN user1 */
1174 _jtag->shiftIR(USER1, 6);
1175 /* send first already stored cmd,
1176 * in the same time store each byte
1177 * to next
1178 */
1179 _jtag->shiftDR(jtx, (rx == NULL)? NULL: jrx, 8*xfer_len);
1180
1181 if (rx != NULL) {
1182 for (uint32_t i=0; i < len; i++)
1183 rx[i] = McsParser::reverseByte(jrx[i+1] >> 1) | (jrx[i+2] & 0x01);
1184 }
1185 return 0;
1186 }
1187
spi_put(uint8_t * tx,uint8_t * rx,uint32_t len)1188 int Xilinx::spi_put(uint8_t *tx, uint8_t *rx, uint32_t len)
1189 {
1190 int xfer_len = len + ((rx == NULL) ? 0 : 1);
1191 uint8_t jtx[xfer_len];
1192 uint8_t jrx[xfer_len];
1193 if (tx != NULL) {
1194 for (uint32_t i=0; i < len; i++)
1195 jtx[i] = McsParser::reverseByte(tx[i]);
1196 }
1197 /* addr BSCAN user1 */
1198 _jtag->shiftIR(USER1, 6);
1199 /* send first already stored cmd,
1200 * in the same time store each byte
1201 * to next
1202 */
1203 _jtag->shiftDR(jtx, (rx == NULL)? NULL: jrx, 8*xfer_len);
1204
1205 if (rx != NULL) {
1206 for (uint32_t i=0; i < len; i++)
1207 rx[i] = McsParser::reverseByte(jrx[i] >> 1) | (jrx[i+1] & 0x01);
1208 }
1209 return 0;
1210 }
1211
spi_wait(uint8_t cmd,uint8_t mask,uint8_t cond,uint32_t timeout,bool verbose)1212 int Xilinx::spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
1213 uint32_t timeout, bool verbose)
1214 {
1215 uint8_t rx[2];
1216 uint8_t dummy[2];
1217 uint8_t tmp;
1218 uint8_t tx = McsParser::reverseByte(cmd);
1219 uint32_t count = 0;
1220
1221 _jtag->shiftIR(USER1, 6, Jtag::UPDATE_IR);
1222 _jtag->shiftDR(&tx, NULL, 8, Jtag::SHIFT_DR);
1223
1224 do {
1225 _jtag->shiftDR(dummy, rx, 8*2, Jtag::SHIFT_DR);
1226 tmp = (McsParser::reverseByte(rx[0]>>1)) | (0x01 & rx[1]);
1227 count++;
1228 if (count == timeout){
1229 printf("timeout: %x %x %x\n", tmp, rx[0], rx[1]);
1230 break;
1231 }
1232 if (verbose) {
1233 printf("%x %x %x %u\n", tmp, mask, cond, count);
1234 }
1235 } while ((tmp & mask) != cond);
1236 _jtag->shiftDR(dummy, rx, 8*2, Jtag::EXIT1_DR);
1237 _jtag->go_test_logic_reset();
1238
1239 if (count == timeout) {
1240 printf("%x\n", tmp);
1241 std::cout << "wait: Error" << std::endl;
1242 return -ETIME;
1243 } else {
1244 return 0;
1245 }
1246 }
1247