1#!/usr/bin/env perl 2if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } 3# DESCRIPTION: Verilator: Verilog Test driver/expect definition 4# 5# Copyright 2003 by Wilson Snyder. This program is free software; you 6# can redistribute it and/or modify it under the terms of either the GNU 7# Lesser General Public License Version 3 or the Perl Artistic License 8# Version 2.0. 9# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 10 11scenarios(vlt_all => 1); 12 13compile( 14 verilator_flags2 => ["--stats"], 15 ); 16 17file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); 18# Important: if reorder succeeded, we should see no dly vars. 19# Equally important: twin test t_alw_noreorder should see dly vars, 20# is identical to this test except for disabling the reorder step. 21foreach my $file ( 22 glob_all("$Self->{obj_dir}/$Self->{VM_PREFIX}*.h"), 23 glob_all("$Self->{obj_dir}/$Self->{VM_PREFIX}*.cpp") 24 ) { 25 file_grep_not($file, qr/dly__t__DOT__v1/i); 26 file_grep_not($file, qr/dly__t__DOT__v2/i); 27 file_grep_not($file, qr/dly__t__DOT__v3/i); 28} 29 30execute( 31 check_finished => 1, 32 ); 33 34ok(1); 351; 36