1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2018 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 integer cyc; initial cyc=1; 14 15 reg [15:0] m_din; 16 17 reg [15:0] v1; 18 reg [15:0] v2; 19 reg [15:0] v3; 20 integer nosplit; 21 22 always @ (posedge clk) begin 23 // write needed so that V3Dead doesn't kill v0..v3 24 $write(" values %x %x %x\n", v1, v2, v3); 25 26 // Locally-set 'nosplit' will prevent the if from splitting 27 // in splitAlwaysAll(). This whole always block should still be 28 // intact when we call splitReorderAll() which is the subject 29 // of this test. 30 nosplit = cyc; 31 if (nosplit > 2) begin 32 /* S1 */ v1 <= 16'h0; 33 /* S2 */ v1 <= m_din; 34 /* S3 */ if (m_din == 16'h0) begin 35 /* X1 */ v2 <= v1; 36 /* X2 */ v3 <= v2; 37 end 38 end 39 40 // We expect to swap S2 and S3, and to swap X1 and X2. 41 // We can check that this worked by the absense of dly vars 42 // in the generated output; if the reorder fails (or is disabled) 43 // we should see dly vars for v1 and v2. 44 end 45 46 always @ (posedge clk) begin 47 if (cyc!=0) begin 48 cyc<=cyc+1; 49 if (cyc==7) begin 50 $write("*-* All Finished *-*\n"); 51 $finish; 52 end 53 end 54 end 55 56endmodule 57