1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty, 2009 by Iztok Jeras.
5// SPDX-License-Identifier: CC0-1.0
6
7//bug991
8module t (/*AUTOARG*/);
9
10   logic [31:0] array_assign [3:0];
11   logic [31:0] array_other [3:0];
12
13   logic [31:0] larray_assign [0:3];
14   logic [31:0] larray_other [0:3];
15
16   initial begin
17      array_assign[0] = 32'd1;
18      array_assign[3:1] = '{32'd4, 32'd3, 32'd2};
19
20      array_other[0] = array_assign[0]+10;
21      array_other[3:1] = array_assign[3:1];
22      if (array_other[0] != 11) $stop;
23      if (array_other[1] != 2) $stop;
24      if (array_other[2] != 3) $stop;
25      if (array_other[3] != 4) $stop;
26
27      larray_assign[0] = 32'd1;
28      larray_assign[1:3] = '{32'd4, 32'd3, 32'd2};
29
30      larray_other[0] = larray_assign[0]+10;
31      larray_other[1:3] = larray_assign[1:3];
32      if (larray_other[0] != 11) $stop;
33      if (larray_other[1] != 4) $stop;
34      if (larray_other[2] != 3) $stop;
35      if (larray_other[3] != 2) $stop;
36
37      $write("*-* All Finished *-*\n");
38      $finish;
39   end
40endmodule
41