1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2007 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 14 reg toggle; 15 16 integer cyc; initial cyc=1; 17 wire [7:0] cyc_copy = cyc[7:0]; 18 19 always @ (negedge clk) begin 20 AssertionFalse1: assert (cyc<100); 21 assert (!(cyc==5) || toggle); 22 // FIX cover {cyc==3 || cyc==4}; 23 // FIX cover {cyc==9} report "DefaultClock,expect=1"; 24 // FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1"; 25 end 26 27 always @ (posedge clk) begin 28 if (cyc!=0) begin 29 cyc <= cyc + 1; 30 toggle <= !cyc[0]; 31 if (cyc==7) assert (cyc[0] == cyc[1]); // bug743 32 if (cyc==9) begin 33`ifdef FAILING_ASSERTIONS 34 assert (0) else $info; 35 assert (0) else $info("Info message"); 36 assume (0) else $info("Info message from failing assumption"); 37 assert (0) else $info("Info message, cyc=%d", cyc); 38 InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); 39 InErrorBlock: assert (0) else $error("Error...."); 40 assert (0) else $fatal(1,"Fatal...."); 41`endif 42 end 43 if (cyc==10) begin 44 $write("*-* All Finished *-*\n"); 45 $finish; 46 end 47 end 48 end 49 50endmodule 51