1// DESCRIPTION: Verilator: Verilog Test module
2//
3// A test case for struct signal bit selection.
4//
5// This test is to check that bit selection of multi-dimensional signal inside
6// of a packed struct works. Currently +: and -: blow up with packed structs.
7//
8// This file ONLY is placed into the Public Domain, for any use, without
9// warranty, 2013 by Jie Xu.
10// SPDX-License-Identifier: CC0-1.0
11
12`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
13
14module t(/*AUTOARG*/
15   // Inputs
16   clk
17   );
18
19   input clk;
20   typedef struct packed {
21       logic [15:0] channel;
22       logic [15:0] others;
23   } buss_t;
24
25   buss_t     b;
26
27   reg [7:0]  a;
28   reg [7:0]  c;
29   reg [7:0]  d;
30
31   union      packed {
32      logic [31:0] [7:0] idx;
33      struct 		     packed {
34	 logic [15:0]      z, y, x;
35	 logic [25:0] [7:0] r;
36      } nam;
37   } gpr;
38
39   reg [14:0] gpr_a;
40
41   initial begin
42      b = {16'h8765,16'h4321};
43      a = b[19:12];			// This works
44      c = b[8+:8];			// This fails
45      d = b[11-:8];			// This fails
46      `checkh(a, 8'h54);
47      `checkh(c, 8'h43);
48      `checkh(d, 8'h32);
49
50      gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345;
51      `checkh (gpr[255:255-14], 15'h091a);
52      gpr_a = gpr.nam.z[15:1];
53      `checkh (gpr_a, 15'h091a);
54
55      $write("*-* All Finished *-*\n");
56      $finish;
57   end
58
59endmodule
60