1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2003 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 14 integer _mode; initial _mode=0; 15 reg [7:0] a; 16 reg [7:0] b; 17 reg [7:0] c; 18 19 reg [7:0] mode_d1r; 20 reg [7:0] mode_d2r; 21 reg [7:0] mode_d3r; 22 23 // surefire lint_off ITENST 24 // surefire lint_off STMINI 25 // surefire lint_off NBAJAM 26 27 always @ (posedge clk) begin // filp-flops with asynchronous reset 28 if (0) begin 29 _mode <= 0; 30 end 31 else begin 32 _mode <= _mode + 1; 33 if (_mode==0) begin 34 $write("[%0t] t_blocking: Running\n", $time); 35 a <= 8'd0; 36 b <= 8'd0; 37 c <= 8'd0; 38 end 39 else if (_mode==1) begin 40 if (a !== 8'd0) $stop; 41 if (b !== 8'd0) $stop; 42 if (c !== 8'd0) $stop; 43 a <= b; 44 b <= 8'd1; 45 c <= b; 46 if (a !== 8'd0) $stop; 47 if (b !== 8'd0) $stop; 48 if (c !== 8'd0) $stop; 49 end 50 else if (_mode==2) begin 51 if (a !== 8'd0) $stop; 52 if (b !== 8'd1) $stop; 53 if (c !== 8'd0) $stop; 54 a <= b; 55 b <= 8'd2; 56 c <= b; 57 if (a !== 8'd0) $stop; 58 if (b !== 8'd1) $stop; 59 if (c !== 8'd0) $stop; 60 end 61 else if (_mode==3) begin 62 if (a !== 8'd1) $stop; 63 if (b !== 8'd2) $stop; 64 if (c !== 8'd1) $stop; 65 end 66 else if (_mode==4) begin 67 if (mode_d3r != 8'd1) $stop; 68 $write("*-* All Finished *-*\n"); 69 $finish; 70 end 71 end 72 end 73 74 always @ (posedge clk) begin 75 mode_d3r <= mode_d2r; 76 mode_d2r <= mode_d1r; 77 mode_d1r <= _mode[7:0]; 78 end 79 80 reg [14:10] bits; 81 // surefire lint_off SEQASS 82 always @ (posedge clk) begin 83 if (_mode==1) begin 84 bits[14:13] <= 2'b11; 85 bits[12] <= 1'b1; 86 end 87 if (_mode==2) begin 88 bits[11:10] <= 2'b10; 89 bits[13] <= 0; 90 end 91 if (_mode==3) begin 92 if (bits !== 5'b10110) $stop; 93 end 94 end 95 96endmodule 97