1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2021 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (clk); 8 input clk; 9 always @(posedge clk) begin 10 $c("const CData xthis = this->clk;"); 11 $c("const CData thisx = xthis;"); 12 $c("const CData xthisx = thisx;"); 13 $c("this->clk = xthisx;"); 14 end 15endmodule 16