1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2005 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 value 10 ); 11 input [3:0] value; 12 always @ (/*AS*/value) begin 13 case (value) 14 default: $stop; 15 4'd0000: $stop; 16 default: $stop; 17 endcase 18 end 19endmodule 20