1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2008 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 integer cyc = 0; 14 reg [63:0] crc; 15 reg [63:0] sum; 16 17 // Take CRC data and apply to testblock inputs 18 wire [1:0] in = crc[1:0]; 19 20 /*AUTOWIRE*/ 21 // Beginning of automatic wires (for undeclared instantiated-module outputs) 22 wire [1:0] out; // From test of Test.v 23 // End of automatics 24 25 Test test (/*AUTOINST*/ 26 // Outputs 27 .out (out[1:0]), 28 // Inputs 29 .in (in[1:0])); 30 31 // Aggregate outputs into a single result vector 32 wire [63:0] result = {62'h0, out}; 33 34 // What checksum will we end up with 35`define EXPECTED_SUM 64'hbb2d9709592f64bd 36 37 // Test loop 38 always @ (posedge clk) begin 39`ifdef TEST_VERBOSE 40 $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); 41`endif 42 cyc <= cyc + 1; 43 crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; 44 sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; 45 if (cyc==0) begin 46 // Setup 47 crc <= 64'h5aef0c8d_d70a4497; 48 end 49 else if (cyc<10) begin 50 sum <= 64'h0; 51 end 52 else if (cyc<90) begin 53 end 54 else if (cyc==99) begin 55 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); 56 if (crc !== 64'hc77bb9b3784ea091) $stop; 57 if (sum !== `EXPECTED_SUM) $stop; 58 $write("*-* All Finished *-*\n"); 59 $finish; 60 end 61 end 62 63endmodule 64 65module Test (/*AUTOARG*/ 66 // Outputs 67 out, 68 // Inputs 69 in 70 ); 71 input [1:0] in; 72 output reg [1:0] out; 73 always @* begin 74 // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked? 75 case (in[1:0]) 76 2'd0, 2'd1, 2'd2, 2'd3: begin 77 out = in; 78 end 79 endcase 80 end 81endmodule 82