1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7typedef class Cls; 8 9class Base; 10 int value = 1; 11 function void test; 12 if (value != 1) $stop; 13 if (this.value != 1) $stop; 14 value = 2; 15 if (value != 2) $stop; 16 this.value = 3; 17 if (value != 3) $stop; 18 endfunction 19endclass 20 21class Cls extends Base; 22 int value = 20; 23 function void test; 24 if (value != 20) $stop; 25 if (this.value != 20) $stop; 26 if (super.value != 1) $stop; 27 28 super.test(); 29 if (this.value != 20) $stop; 30 31 super.value = 9; 32 this.value = 29; 33 if (super.value != 9) $stop; 34 if (value != 29) $stop;; 35 endfunction 36endclass 37 38module t (/*AUTOARG*/); 39 initial begin 40 Cls c; 41 c = new; 42 c.test(); 43 $write("*-* All Finished *-*\n"); 44 $finish; 45 end 46endmodule 47