1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7// verilator lint_off MULTITOP 8 9module M; 10class Cls; 11 function string name; 12 return $sformatf("m %m"); 13 endfunction 14endclass 15endmodule 16 17module t (/*AUTOARG*/); 18 string s; 19 20 initial begin 21 M::Cls p; 22 $write("*-* All Finished *-*\n"); 23 $finish; 24 end 25endmodule 26