1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 Rafal Kapuscik
5// SPDX-License-Identifier: CC0-1.0
6//
7
8module t(/*AUTOARG*/
9   // Inputs
10   clk
11   );
12   input clk;
13   bit [3:0] addr;
14   initial begin
15      super.addr = 2;
16      $write("*-* All Finished *-*\n");
17      $finish;
18   end
19endmodule
20