1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7// Parse check
8class uvm_resource_types;
9   typedef int rsrc_q_t;
10endclass
11class uvm_resource_pool;
12   uvm_resource_types::rsrc_q_t rtab [string];
13
14   uvm_resource_types#(1,2,3)::rsrc_q_t rtab_paramed [string];
15endclass
16
17module t (/*AUTOARG*/);
18   initial begin
19      $write("*-* All Finished *-*\n");
20      $finish;
21   end
22endmodule
23