1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 Rafal Kapuscik
5// SPDX-License-Identifier: CC0-1.0
6//
7class Cls;
8   bit [3:0] addr;
9   function void set(bit [3:0] addr);
10   begin : body
11     this.addr = addr;
12   end : body
13   endfunction
14   extern function void setext(bit [3:0] addr);
15endclass
16
17function void Cls::setext(bit [3:0] addr);
18   this.addr = addr;
19endfunction
20
21module t(/*AUTOARG*/
22   // Inputs
23   clk
24   );
25   input clk;
26   Cls bar;
27   Cls baz;
28   initial begin
29      bar = new();
30      baz = new();
31      bar.set(4);
32`ifdef TEST_VERBOSE
33      $display(bar.addr);
34      $display(baz.addr);
35`endif
36      if (bar.addr != 4) $stop;
37      bar.setext(2);
38      if (bar.addr != 2) $stop;
39      $write("*-* All Finished *-*\n");
40      $finish;
41   end
42endmodule
43