1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t(/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 integer cyc = 0; 14 reg [1:0] reg_i; 15 reg [1049:0] pad0; 16 reg [1049:0] reg_o; 17 reg [1049:0] spad1; 18 19 /*AUTOWIRE*/ 20 21 always_comb begin 22 if (reg_i[1] == 1'b1) 23 reg_o = {986'd0, 64'hffff0000ffff0000}; 24 else if (reg_i[0] == 1'b1) 25 reg_o = {64'hffff0000ffff0000, 986'd0}; 26 else 27 reg_o = 1050'd0; 28 end 29 30 // Test loop 31 always @ (posedge clk) begin 32 cyc <= cyc + 1; 33 if (cyc == 0) begin 34 reg_i <= 2'b00; 35 pad0 <= '1; 36 spad1 <= '1; 37 end 38 else if (cyc == 1) begin 39 reg_i <= 2'b01; 40 end 41 else if (cyc == 2) begin 42 if (reg_o != {64'hffff0000ffff0000, 986'd0}) $stop; 43 reg_i <= 2'b10; 44 end 45 else if (cyc == 99) begin 46 if (reg_o != {986'd0, 64'hffff0000ffff0000}) $stop; 47 if (pad0 != '1) $stop; 48 if (spad1 != '1) $stop; 49 $write("*-* All Finished *-*\n"); 50 $finish; 51 end 52 end 53endmodule 54