1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2003 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t; 8 reg [40:0] disp; initial disp = 41'ha_bbbb_cccc; 9 initial begin 10 // Display formatting 11 $display("%x"); // Too few 12 $display("%x",disp,disp); // Too many 13 $display("%q"); // Bad escape 14 $write("*-* All Finished *-*\n"); 15 $finish; 16 end 17endmodule 18