1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2019 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t;
8   initial begin
9      $display("\x\y\z");  // Illegal escapes
10   end
11endmodule
12