1// DESCRIPTION: Verilator: Verilog Test module 2// 3// Copyright 2009 by Wilson Snyder. This program is free software; you can 4// redistribute it and/or modify it under the terms of either the GNU 5// Lesser General Public License Version 3 or the Perl Artistic License 6// Version 2.0. 7// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 8 9`ifdef VCS 10 `define NO_SHORTREAL 11`endif 12`ifdef NC 13 `define NO_SHORTREAL 14`endif 15`ifdef VERILATOR // Unsupported 16 `define NO_SHORTREAL 17`endif 18 19module t (/*AUTOARG*/); 20 21 // Note these are NOT pure. 22 import "DPI-C" function int dpii_clear (); 23 import "DPI-C" function int dpii_count (input int ctr); 24 import "DPI-C" function bit dpii_inc0 (input int ctr); 25 import "DPI-C" function bit dpii_inc1 (input int ctr); 26 import "DPI-C" function bit dpii_incx (input int ctr, input bit value); 27 28 integer i; 29 integer j; 30 integer k; 31 bit b; 32 integer errors; 33 34 task check1(integer line, bit got, bit ex); 35 if (got != ex) begin 36 $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); 37 errors++; 38 end 39 endtask 40 task check(integer line, int got, int ex); 41 if (got != ex) begin 42 $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); 43 errors++; 44 end 45 endtask 46 47 // Test loop 48 initial begin 49 // bug963 50 // verilator lint_off IGNOREDRETURN 51 dpii_clear(); 52 // verilator lint_on IGNOREDRETURN 53 j = 0; 54 for (i=0; i<64; i++) begin 55 if (i[0]) 56 j = 0; 57 else 58 j = {31'b0, dpii_inc1(0)}; 59 k = k + j; 60 end 61 $write("%x\n",k); 62 check (`__LINE__, dpii_count(0), 32); 63 64 if (|errors) $stop; 65 $write("*-* All Finished *-*\n"); 66 $finish; 67 end 68 69endmodule 70