1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2009 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 14 enum integer { 15 16 EP_State_IDLE , 17 EP_State_CMDSHIFT0 , 18 EP_State_CMDSHIFT13 , 19 EP_State_CMDSHIFT14 , 20 EP_State_CMDSHIFT15 , 21 EP_State_CMDSHIFT16 , 22 EP_State_DWAIT , 23 EP_State_DSHIFT0 , 24 EP_State_DSHIFT1 , 25 EP_State_DSHIFT15 } m_state_xr, m_state2_xr; 26 27 // Beginning of automatic ASCII enum decoding 28 reg [79:0] m_stateAscii_xr; // Decode of m_state_xr 29 always @(m_state_xr) begin 30 case ({m_state_xr}) 31 EP_State_IDLE: m_stateAscii_xr = "idle "; 32 EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; 33 EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; 34 EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; 35 EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; 36 EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; 37 EP_State_DWAIT: m_stateAscii_xr = "dwait "; 38 EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; 39 EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; 40 EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; 41 default: m_stateAscii_xr = "%Error "; 42 endcase 43 end 44 // End of automatics 45 46 integer cyc; initial cyc=1; 47 always @ (posedge clk) begin 48 if (cyc!=0) begin 49 cyc <= cyc + 1; 50 //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); 51 if (cyc==1) begin 52 m_state_xr <= EP_State_IDLE; 53 m_state2_xr <= EP_State_IDLE; 54 end 55 if (cyc==2) begin 56 if (m_stateAscii_xr != "idle ") $stop; 57 m_state_xr <= EP_State_CMDSHIFT13; 58 if (m_state2_xr != EP_State_IDLE) $stop; 59 m_state2_xr <= EP_State_CMDSHIFT13; 60 end 61 if (cyc==3) begin 62 if (m_stateAscii_xr != "cmdshift13") $stop; 63 m_state_xr <= EP_State_CMDSHIFT16; 64 if (m_state2_xr != EP_State_CMDSHIFT13) $stop; 65 m_state2_xr <= EP_State_CMDSHIFT16; 66 end 67 if (cyc==4) begin 68 if (m_stateAscii_xr != "cmdshift16") $stop; 69 m_state_xr <= EP_State_DWAIT; 70 if (m_state2_xr != EP_State_CMDSHIFT16) $stop; 71 m_state2_xr <= EP_State_DWAIT; 72 end 73 if (cyc==9) begin 74 if (m_stateAscii_xr != "dwait ") $stop; 75 if (m_state2_xr != EP_State_DWAIT) $stop; 76 $write("*-* All Finished *-*\n"); 77 $finish; 78 end 79 end 80 end 81 82endmodule 83